Datasheet

Signal Description
56 Datasheet, Volume 1
6.2 Memory Reference and Compensation
6.3 Reset and Miscellaneous Signals
Table 6-4. Memory Reference and Compensation
Signal Name Description Direction Type
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
Channel A and B Output DDR3 DIMM DQ Reference Voltage.
OAnalog
SM_RCOMP[2:0] System Memory Impedance Compensation. I Analog
Table 6-5. Reset and Miscellaneous Signals (Sheet 1 of 2)
Signal Name Description Direction Type
CFG[17:0]
Configuration signals:
The CFG signals have a default value of 1 if not
terminated on the board.
• CFG[0]: PCI Express Bifurcation:
— With all Intel
®
5 Series Chipsets except P55
and P57 SKUs
—Reserved (Only 1 x16 PCI Express
supported by default)
— With workstation Intel 3400 Series Chipset:
—1 = 1 x16 PCI Express
—0 = 2 x8 PCI Express
• CFG[1]: Reserved (Intel Core™ i5 processor PCI
Express Port Bifurcation)
• CFG[2]: Reserved configuration lands. A test point
may be placed on the board for this land.
• CFG[3]: PCI Express* Static Lane Numbering
Reversal. A test point may be placed on the board
for this land. Lane reversal will be applied across all
16 lanes.
—1 = No Reversal
—0 = Reversal
In the case of Bifurcation with NO Lane Reversal,
the physical lane mapping is as follows:
— Lanes 15:8 => Port 1 Lanes 7:0
— Lanes 7:0 => Port 0 Lanes 7:0
In the case of Bifurcation With Lane Reversal, the
physical lane mapping is as follows:
— Lanes 15:8 => Port 0 Lanes 0:7
— Lanes 7:0 => Port 1 Lanes 0:7
• CFG[6:4]: Reserved configuration lands. A test
point may be placed on the board for this land.
• CFG[17:7]: Reserved configuration lands. Intel
does not recommend a test point on the board for
this land.
ICMOS
COMP0
Impedance compensation must be terminated on the
system board using a precision resistor. Refer to
Table 7-11 for the termination requirement.
IAnalog
COMP1
Impedance compensation must be terminated on the
system board using a precision resistor. Refer to
Table 7-11 for the termination requirement.
IAnalog