Datasheet

Datasheet, Volume 1 5
6 Signal Description ...................................................................................................53
6.1 System Memory Interface ..................................................................................54
6.2 Memory Reference and Compensation..................................................................56
6.3 Reset and Miscellaneous Signals..........................................................................56
6.4 PCI Express* Based Interface Signals...................................................................58
6.5 DMI—Processor to PCH Serial Interface ................................................................58
6.6 PLL Signals.......................................................................................................58
6.7 Intel
®
Flexible Display Interface Signals...............................................................59
6.8 JTAG/ITP Signals...............................................................................................59
6.9 Error and Thermal Protection ..............................................................................60
6.10 Power Sequencing.............................................................................................61
6.11 Processor Core Power Signals .............................................................................61
6.12 Graphics and Memory Core Power Signals.............................................................63
6.13 Ground and NCTF..............................................................................................63
6.14 Processor Internal Pull Up/Pull Down....................................................................64
7 Electrical Specifications...........................................................................................65
7.1 Power and Ground Lands....................................................................................65
7.2 Decoupling Guidelines........................................................................................65
7.2.1 Voltage Rail Decoupling...........................................................................65
7.3 Processor Clocking (BCLK[0], BCLK#[0])..............................................................66
7.3.1 PLL Power Supply...................................................................................66
7.4 V
CC
Voltage Identification (VID) ..........................................................................66
7.5 Graphics Voltage Identification (GFX_VID)............................................................67
7.6 Reserved or Unused Signals................................................................................70
7.7 Signal Groups...................................................................................................70
7.8 Test Access Port (TAP) Connection.......................................................................73
7.9 Absolute Maximum and Minimum Ratings .............................................................73
7.10 DC Specifications ..............................................................................................74
7.10.1 Voltage and Current Specifications............................................................74
7.11 Platform Environmental Control Interface (PECI) DC Specifications...........................82
7.11.1 DC Characteristics..................................................................................82
7.11.2 Input Device Hysteresis ..........................................................................83
8 Processor Land and Signal Information ...................................................................85
8.1 Processor Land Assignments...............................................................................85
Figures
1-1 Intel
®
Core™ i5-600, i3-500 Desktop Processor Series and Intel
®
Pentium
®
Desktop
Processor 6000 Series Platform Diagram..................................................................... 10
2-1 Intel
®
Flex Memory Technology Operation...................................................................21
2-2 Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes ..................22
2-3 PCI Express* Layering Diagram .................................................................................24
2-4 Packet Flow through the Layers .................................................................................25
2-5 PCI Express Related Register Structures in the Processor ..............................................26
2-6 Processor Graphic Processing Unit Block Diagram.........................................................28
2-7 Processor Display Block Diagram................................................................................31
4-1 Idle Power Management Breakdown of the Processor Cores ...........................................42
4-2 Thread and Core C-State Entry and Exit......................................................................42
4-3 Package C-State Entry and Exit..................................................................................46
7-1 V
CC
Static and Transient Tolerance Loadlines ...............................................................77
7-2 V
AXG
Static and Transient Tolerance Loadlines .............................................................78
7-3 Input Device Hysteresis ............................................................................................83
8-1 Socket Pinmap (Top View, Upper-Left Quadrant)..........................................................85