Datasheet
4 Datasheet, Volume 1
2.4.2.1 Display Planes ..........................................................................31
2.4.2.2 Display Pipes............................................................................32
2.4.2.3 Display Ports ............................................................................32
2.4.3 Intel
®
Flexible Display Interface ...............................................................32
2.5 Platform Environment Control Interface (PECI) ......................................................33
2.6 Interface Clocking..............................................................................................33
2.6.1 Internal Clocking Requirements ................................................................33
3 Technologies............................................................................................................35
3.1 Intel
®
Virtualization Technology ..........................................................................35
3.1.1 Intel
®
VT-x Objectives ............................................................................35
3.1.2 Intel
®
VT-x Features...............................................................................35
3.1.3 Intel
®
VT-d Objectives ............................................................................36
3.1.4 Intel
®
VT-d Features...............................................................................36
3.1.5 Intel
®
VT-d Features Not Supported..........................................................37
3.2 Intel
®
Trusted Execution Technology (Intel
®
TXT) .................................................37
3.3 Intel
®
Hyper-Threading Technology .....................................................................38
3.4 Intel
®
Turbo Boost Technology............................................................................38
3.5 New Instructions ...............................................................................................38
3.5.1 Advanced Encryption Standard New Instructions (AESNI).............................38
3.5.2 PCLMULQDQ Instruction ..........................................................................38
4 Power Management .................................................................................................39
4.1 ACPI States Supported.......................................................................................39
4.1.1 System States........................................................................................39
4.1.2 Processor Core/Package Idle States...........................................................39
4.1.3 Integrated Memory Controller States.........................................................39
4.1.4 PCI Express* Link States .........................................................................40
4.1.5 Integrated Graphics States ......................................................................40
4.1.6 Interface State Combinations ...................................................................40
4.2 Processor Core Power Management......................................................................41
4.2.1 Enhanced Intel
®
SpeedStep
®
Technology ..................................................41
4.2.2 Low-Power Idle States.............................................................................41
4.2.3 Requesting Low-Power Idle States ............................................................43
4.2.4 Core C-states.........................................................................................44
4.2.4.1 Core C0 State...........................................................................44
4.2.4.2 Core C1/C1E State ....................................................................44
4.2.4.3 Core C3 State...........................................................................44
4.2.4.4 Core C6 State...........................................................................44
4.2.4.5 C-State Auto-Demotion..............................................................45
4.2.5 Package C-States ...................................................................................45
4.2.5.1 Package C0 ..............................................................................46
4.2.5.2 Package C1/C1E........................................................................47
4.2.5.3 Package C3 State......................................................................47
4.2.5.4 Package C6 State......................................................................47
4.3 Integrated Memory Controller (IMC) Power Management.........................................48
4.3.1 Disabling Unused System Memory Outputs.................................................48
4.3.2 DRAM Power Management and Initialization ...............................................48
4.3.2.1 Initialization Role of CKE ............................................................48
4.3.2.2 Conditional Self-Refresh.............................................................48
4.3.2.3 Dynamic Power Down Operation..................................................49
4.3.2.4 DRAM I/O Power Management ....................................................49
4.4 PCI Express* Power Management ........................................................................49
4.5 Integrated Graphics Power Management...............................................................50
4.5.1 Graphics Render C-State .........................................................................50
5 Thermal Management ..............................................................................................51