Datasheet

8 Datasheet, Volume 1
4-11 Coordination of Core Power States at the Package Level ..............................................59
4-12 Targeted Memory State Conditions............................................................................64
5-1 Intel
®
Turbo Boost Technology Package Power Control Settings....................................71
5-2 Configurable Thermal Design Power (cTDP) Modes ......................................................73
5-3 Thermal Design Power (TDP) Specifications................................................................75
5-4 Junction Temperature Specification...........................................................................75
5-5 Package Turbo Parameters.......................................................................................76
5-6 Idle Power Specifications .........................................................................................77
6-1 Signal Description Buffer Types ................................................................................85
6-2 Memory Channel A Signals.......................................................................................86
6-3 Memory Channel B Signals.......................................................................................87
6-4 Memory Reference and Compensation.......................................................................88
6-5 Reset and Miscellaneous Signals...............................................................................88
6-6 PCI Express* Graphics Interface Signals ....................................................................89
6-7 Embedded DisplayPort* Signals................................................................................89
6-8 Intel
®
Flexible Display (Intel
®
FDI) Interface .............................................................89
6-9 Direct Media Interface (DMI) Signals – Processor to PCH Serial Interface........................90
6-10 Phase Lock Loop (PLL) Signals..................................................................................90
6-11 Test Access Points (TAP) Signals...............................................................................90
6-12 Error and Thermal Protection Signals.........................................................................91
6-13 Power Sequencing Signals .......................................................................................92
6-14 Processor Power Signals ..........................................................................................93
6-15 Sense Signals ........................................................................................................93
6-16 Ground and Non-Critical to Function (NCTF) Signals ....................................................94
6-17 Processor Internal Pull-Up / Pull-Down Resistors.........................................................94
7-1 IMVP7 Voltage Identification Definition ......................................................................96
7-2 VCCSA_VID Configuration........................................................................................99
7-3 Signal Groups1.....................................................................................................100
7-4 Storage Condition Ratings......................................................................................102
7-5 Processor Core (V
CC
) Active and Idle Mode DC Voltage and Current Specifications.........103
7-6 Processor Uncore (V
CCIO
) Supply DC Voltage and Current Specifications.......................105
7-7 Memory Controller (V
DDQ
) Supply DC Voltage and Current Specifications .....................105
7-8 System Agent (V
CCSA
) Supply DC Voltage and Current Specifications...........................105
7-9 Processor PLL (VCCPLL) Supply DC Voltage and Current Specifications.........................106
7-10 Processor Graphics (V
AXG
) Supply DC Voltage and Current Specifications .....................106
7-11 DDR3 / DDR3L / DDR3L-RS Signal Group DC Specifications........................................107
7-12 Control Sideband and TAP Signal Group DC Specifications..........................................108
7-13 PCI Express* DC Specifications...............................................................................109
7-14 Embedded DisplayPort* DC Specifications................................................................109
7-15 PECI DC Electrical Limits........................................................................................111
8-1 rPGA988B Processor Pin List by Pin Name ................................................................114
8-2 BGA1224 Processor Ball List by Ball Name ...............................................................127
8-3 BGA1023 Processor Ball List by Ball Name ...............................................................146
9-1 DDR Data Swizzling Table – Channel A ....................................................................170
9-2 DDR Data Swizzling Table for Package – Channel B...................................................171