Datasheet
6 Datasheet, Volume 1
5.6.2 Digital Thermal Sensor ............................................................................80
5.6.2.1 Digital Thermal Sensor Accuracy (Taccuracy) ................................81
5.6.2.2 Fan Speed Control with Digital Thermal Sensor .............................81
5.6.3 PROCHOT# Signal ..................................................................................81
5.6.3.1 Bi-Directional PROCHOT#...........................................................81
5.6.3.2 Voltage Regulator Protection versus PROCHOT#............................82
5.6.3.3 Thermal Solution Design and PROCHOT# Behavior ........................82
5.6.3.4 Low-Power States and PROCHOT# Behavior..................................82
5.6.3.5 THERMTRIP# Signal ..................................................................83
5.6.3.6 Critical Temperature Detection....................................................83
5.6.4 On-Demand Mode...................................................................................83
5.6.4.1 MSR Based On-Demand Mode.....................................................83
5.6.4.2 I/O Emulation-Based On-Demand Mode .......................................83
5.6.5 Memory Thermal Management..................................................................84
5.6.6 Platform Environment Control Interface (PECI) ...........................................84
6 Signal Description....................................................................................................85
6.1 System Memory Interface Signals........................................................................86
6.2 Memory Reference and Compensation Signals .......................................................88
6.3 Reset and Miscellaneous Signals ..........................................................................88
6.4 PCI Express*-based Interface Signals...................................................................89
6.5 Embedded DisplayPort* (eDP*) Signals ................................................................89
6.6 Intel
®
Flexible Display (Intel
®
FDI) Interface Signals..............................................89
6.7 Direct Media Interface (DMI) Signals....................................................................90
6.8 Phase Lock Loop (PLL) Signals.............................................................................90
6.9 Test Access Points (TAP) Signals..........................................................................90
6.10 Error and Thermal Protection Signals....................................................................91
6.11 Power Sequencing Signals...................................................................................92
6.12 Processor Power Signals .....................................................................................93
6.13 Sense Signals....................................................................................................93
6.14 Ground and Non-Critical to Function (NCTF) Signals ...............................................94
6.15 Processor Internal Pull-Up / Pull-Down Resistors ....................................................94
7 Electrical Specifications ...........................................................................................95
7.1 Power and Ground Pins.......................................................................................95
7.2 Decoupling Guidelines ........................................................................................95
7.2.1 Voltage Rail Decoupling...........................................................................95
7.2.2 PLL Power Supply ...................................................................................95
7.3 Voltage Identification (VID).................................................................................96
7.4 System Agent (SA) Vcc VID ................................................................................99
7.5 Reserved or Unused Signals................................................................................99
7.6 Signal Groups .................................................................................................100
7.7 Test Access Port (TAP) Connection.....................................................................102
7.8 Component Storage Condition Specifications (Prior to Board Attach).......................102
7.9 DC Specifications.............................................................................................103
7.9.1 Voltage and Current Specifications ..........................................................103
7.10 Platform Environmental Control Interface (PECI) DC Specifications.........................110
7.10.1 PECI Bus Architecture............................................................................110
7.10.2 PECI DC Characteristics.........................................................................111
7.10.3 Input Device Hysteresis.........................................................................111
8 Processor Pin, Signal, and Package Information ....................................................113
8.1 Processor Pin Assignments................................................................................113
8.2 Package Mechanical Information........................................................................160
9 DDR Data Swizzling................................................................................................169