Technical information

Chapter 4 56
48h Patterns written in base memory. Determining the amount of memory below
1MB next.
49h The amount of memory below 1MB has been found and verified. Determining
the amount of memory above 1MB memory test.
4Bh The amount of memory above 1Mb has been found and verified. Checking for a
soft reset and clearing the memory below 1MB for the soft reset next.
If this is a power on situation, going to checkpoint 4Eh next.
4Ch The memory below 1MB has been cleared via a soft reset. Clearing the memory
above 1MB next.
4Dh The memory above 1MB has been cleared via a soft reset. Saving the memory
size next. Going to checkpoint 52h next.
4Eh The memory test started, but not as the result of a soft reset. Displaying the
first64KB memory size next.
4Fh The memory size display has started. The display is updated during the memory
test. Performing the sequential and random memory test next.
50h The memory below 1 MB has been tested and initialized. Adjusting the
displayed memory size for relocation and shadowing next.
51h The memory size display was adjusted for relocation and shadowing. Testing
the memory above 1MB next.
52h The memory above 1MB has been tested and initialized. Saving the memory
size information next.
53h The memory size information and the CPU registers are saved. Entering real
mode next.
54h Shutdown was successful. The CPU is in real mode. Disabling the Gate A20
line, parity, and the NMI next.
57h The A20 address line, parity, and the NMI are disabled. Adjusting the memory
size depending on relocation and shadowing next.
58h The memory size was adjusted for relocation and shadowing. Clearing the Hit
< DEL> message next.
59h The Hit < DEL > message is cleared. The < WAIT...> message is displayed.
Starting the DMA and interrupt controller test next.
60h The DMA page register test passed. Performing the DMA Controller 1 base
register test next.
62h The DMA controller 1 base register test passed. Performing the DMA controller
2 base register test next.
65h The DMA controller 2 base register test passed. Programming DMA controllers
1 and 2 next.
66h Completed programming DMA controllers 1 and 2. Initializing the 8259 interrupt
controller next.
67h Completed 8259 interrupt controller initialization.
7Fh Extended NMI source enabling is in progress.
80h The keyboard test has started. Clearing the output buffer and checking for stuck
keys. Issuing the keyboard reset command next.
81h A keyboard reset error or stuck key was found. Issuing the keyboard controller
interface test command next.
82h The keyboard controller interface test completed. Writing the command byte and
initializing the circular buffer next.
Checkpoint Code Description