Technical information

14 Chapter 1
Hardware Specifications and Configurations
PCI Bus Subsystem
PCI Addressing Mapping
The table below summarizes the assignments of IDSEL pins and the PCI addresses of all PCI devices,
and the figure shows the locations of all PCI devices.
System PCI REQ/GNT
The PCI 32-bit arbiters built in CNB20HE_SL. The PCI 64-bit arbiters built in CIOB20. The following
table identifies the mapping of each individual device and REQ/GNT Usage:
PCI Device No. Map
PCI Bus No. Device No. AD No. ( H.W.)
RAGE_XL_A 0 14 D_AD30
BCM5702 0 2 D_AD18
PCI_SLOT5 0 4 D_AD20
PCI_SLOT6 0 6 D_AD22
SCSI_LSI1020 1 4 P_AD20
PCI_SLOT1 1 2 P_AD18
PCI_SLOT2 1 6 P_AD22
PCI_SLOT3 2 2 S_AD18
PCI_SLOT4 2 4 S_AD20
PCI Device Arbitrate & Clock No. map
Clock chip-ICS932S203/Cypress CY28329
Request No. Grant No. Clock No.
RAGE_XL_A -PCIREQ4 -PCIGNT4 VGA_PCLK
BCM5702 -PCIREQ0 -PCIGNT0 540_PCICLK
SCSI_LSI1020 -P_REQ2 -P_GNT2 SCSI_PCICLK
PCI_SLOT1 -P_REQ0 -P_GNT0 PCICLK_SLT1
PCI_SLOT2 -P_REQ1 -P_GNT1 PCICLK_SLT2
PCI_SLOT3 -S_REQ0 -S_GNT0 PCICLK_SLT3
PCI_SLOT4 -S_REQ1 -S_GNT1 PCICLK_SLT4
PCI_SLOT5 -PCIREQ1 -PCIGNT1 PCICLK_SLT5
PCI_SLOT6 -PCIREQ2 -PCIGNT2 PCICLK_SLT6