User`s manual
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EIP_MEM1.SCH
Am486 MICROPROCESSOR
PCI CUSTOMER DEVELOPMENT PLATFORM
EIPCNTL.JED REV. 0.9
Makes 2 banks of 1Mx32 Flash ROM appear as 1 bank of 2Mx32 DRAM (70ns, FPM) to M1489 Memory
Controller. Program M1489 for 2Mx8 (11/10) DRAM chips. MA8 (CPU A22) used as Flash ROM
Bank Select when RAS3# asserted by M1489 Memory Controller.
PAL
4 ea. 1Mx8
Flash ROM Chips
4 ea. 1Mx8
Flash ROM Chips
Bank1 Cntl.
Bank2 Cntl.
VA(2:21)
VA(22)
Am486
MICROPROCESSOR
A(2:22)
’ABT244
A(22)=0
A(22)=1
CPU Address Bit A(22) Used As Flash Bank Select
PLACE THEVENIN TERMINATOR
NEAR 22V10 PAL
Supports burst Read Cycles or single-beat Read Cycles
Access as 32-bits wide always
Set M1489 Memory Controller to "Fast" for proper operation, even if installed DRAM is 60ns and can run at the "Fastest" setting
Supports single-beat Write Cycles only; no back-to-back Write Cycles
Compatible with CAS-before-RAS Refresh Cycles only
Limitations and Operation of the EIP Interface:
Flash chip A0 pin tied to Am486 Microprocessor A2 pin, so multiply desired Flash chip address by 4h to find Am486 Microprocessor address
needed to access the desired memory cell (ex: Flash Chip AAAh accessed by Am486 Microprocessor at 2AA8h)
EIP Flash Array start address moves, depending on how much DRAM is installed (ex: 48MByte DRAM puts EIP start address
at 48MB or 3000000h for first bank of Flash ROMs and 3400000h start address for second bank of Flash ROMs
Uses 29F800T, 55ns devices in "Byte" mode
Accessable from Am486 Microprocessor only; not accessable from PCI Bus Masters
Uses fourth DRAM bank of M1489 Memory Controller
EIP FLASH MEMORY CONTROLLER
2.1
(C) Advanced Micro Devices, Inc. (800) 222-9323
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
926
Friday, December 04, 1998
Title
Size Document Number Rev
Date: Sheet of
REFCIP
WRCIP
MRASJ3
MCASJ3
MCASJ2
VWRJ
MCASJ1
MCASJ0
VCPUCLK1
EIPCE1#
EIPCE2#
EIPOE1#
EIPOE2#
EIPWE2#
AMA8
EIPWE1#
VGA22
RSTDRV
VCC
R158
330
R159
470
U60
PALCE22V10_PLCC (5ns)
2
3
4
5
6
7
9
10
11
12
13
27
26
25
24
23
21
20
19
18
1716
CLK/I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I/O9
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0I11