User`s manual

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SIMM_SKTS.SCH
Am486 MICROPROCESSOR
PCI CUSTOMER DEVELOPMENT PLATFORM
SIMM0 SIMM1 SIMM2
SINGLE BANK SINGLE BANK SINGLE BANK
SINGLE BANKDOUBLE BANK
SIMM SOCKET POPULATION CHART
SIMMS CAN BE SINGLE BANK OR DOUBLE BANK, USING
1Mbit, 4Mbit, or 16Mbit DRAM CHIPS. POPULATE
SIMM SOCKETS AS SHOWN IN THIS CHART.
DRAM 72-PIN SIMM SOCKETS
2.1
(C) Advanced Micro Devices, Inc. [phone]
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
826 Friday, December 04, 1998
Title
Size Document Number Rev
Date: Sheet of
GD31
GD30
GD29
GD28
GD27
GD26
GD25
GD24
GD23
GD22
GD21
GD20
GD19
GD18
GD17
GD16
GD15
GD14
GD13
GD12
GD11
GD10
GD9
GD8
GD7
GD6
GD5
GD4
GD3
GD2
GD1
GD0
MCASJ3
MCASJ2 MDP3
MCASJ1 MDP2
MCASJ0 MDP1
MDP0
AMA10
AMA11
GD [0..31]
MCASJ[0..3]
MDP[0..3]
AM A[0..11]
GD31
GD30
GD29
GD28
GD27
GD26
GD25
GD24
GD23
GD22
GD21
GD20
GD19
GD18
GD17
GD16
GD15
GD14
GD13
GD12
GD11
GD10
GD9
GD8
GD7
GD6
GD5
GD4
GD3
GD2
GD1
GD0
MCASJ3
MCASJ2 MDP3
MCASJ1 MDP2
MCASJ0 MDP1
MDP0
MDP2
GD26
GD27
GD21
GD8
GD16
GD25
GD17
MCASJ0
GD0
GD1
GD3
GD5
MDP3
GD6
GD11
GD15
GD2
GD22
MCASJ2
GD10
GD28
MDP1
MCASJ3
GD4
GD29
GD12
GD14
GD30
GD7
MDP0
GD20
GD31
MCASJ1
GD13
GD19
GD9
GD24
GD18
GD23
AMA11
AMA10
AMA1
AMA10
AMA0
AMA2
AMA3
AMA4
AMA8
AMA9
AMA5
AMA6
AMA7
AMA11
GD [0..31]
MCASJ[0..3]
MDP[0..3]
MDP[0..3]
MCASJ[0..3]
GD [0..31]
AM A[0..11]
AM A[0..11]
AMA2
AMA5
AMA9
AMA0
AMA4
AMA7
AMA3
AMA8
AMA6
AMA1
AMA3
AMA9
AMA5
AMA4
AMA2
AMA1
AMA8
AMA0
AMA6
AMA7
MDP[0..3]
GD[0..31]
MDP[0..3]
GD[0..31]
MDP[0..3]
GD[0..31]
MWEJ1
AMA[0..11]
MRASJ2
MRASJ1
MCASJ[0..3]
MWEJ0
MRASJ1
MRASJ0
MCASJ[0..3]
MCASJ[0..3]
MRASJ0
AMA[0..11]
MWEJ2
MRASJ2
AMA[0..11]
VCC
VCC
VCC
SIMM1
SIMM72
64
62
60
58
56
54
52
50
27
25
23
21
9
7
5
3
65
63
61
57
55
53
51
49
26
24
22
20
8
6
4
2
38
35
37
36
66
48
46
11
69
68
67
34
45
44
41
43
40
10 30 59
1 39 72
70
33
42
47
71
29
19
32
31
28
18
17
16
15
14
13
12
IO34
IO33
IO32
IO31
IO30
IO29
IO28
IO27
IO25
IO24
IO23
IO22
IO21
IO20
IO19
IO18
IO16
IO15
IO14
IO13
IO12
IO11
IO10
IO9
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
IO35
IO26
IO17
IO8
NC4
NC3
NC2
NC1
PRD2
PRD1
PRD0
RAS2
RAS1
RAS0
CAS2
CAS1
CAS0
VCC VCC VCC
GND GND GND
PRD3
RAS3
CAS3
WE
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
SIMM2
SIMM72
64
62
60
58
56
54
52
50
27
25
23
21
9
7
5
3
65
63
61
57
55
53
51
49
26
24
22
20
8
6
4
2
38
35
37
36
66
48
46
11
69
68
67
34
45
44
41
43
40
10 30 59
1 39 72
70
33
42
47
71
29
19
32
31
28
18
17
16
15
14
13
12
IO34
IO33
IO32
IO31
IO30
IO29
IO28
IO27
IO25
IO24
IO23
IO22
IO21
IO20
IO19
IO18
IO16
IO15
IO14
IO13
IO12
IO11
IO10
IO9
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
IO35
IO26
IO17
IO8
NC4
NC3
NC2
NC1
PRD2
PRD1
PRD0
RAS2
RAS1
RAS0
CAS2
CAS1
CAS0
VCC VCC VCC
GND GND GND
PRD3
RAS3
CAS3
WE
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
SIMM0
SIMM72
64
62
60
58
56
54
52
50
27
25
23
21
9
7
5
3
65
63
61
57
55
53
51
49
26
24
22
20
8
6
4
2
38
35
37
36
66
48
46
11
69
68
67
34
45
44
41
43
40
10 30 59
1 39 72
70
33
42
47
71
29
19
32
31
28
18
17
16
15
14
13
12
IO34
IO33
IO32
IO31
IO30
IO29
IO28
IO27
IO25
IO24
IO23
IO22
IO21
IO20
IO19
IO18
IO16
IO15
IO14
IO13
IO12
IO11
IO10
IO9
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
IO35
IO26
IO17
IO8
NC4
NC3
NC2
NC1
PRD2
PRD1
PRD0
RAS2
RAS1
RAS0
CAS2
CAS1
CAS0
VCC VCC VCC
GND GND GND
PRD3
RAS3
CAS3
WE
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0