User`s manual

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B B
C C
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CPU_VIS1.SCH
HP Conn.
12
19 20
Top View
Am486 MICROPROCESSOR
PCI CUSTOMER DEVELOPMENT PLATFORM
POD 3
POD 4
POD 7
SIGNALS NOT NEEDED BY HP DISASSEMBLER
Using Logic Analyzer Headers:
Clock the analyzer off the clock signal on P41 (POD1)
Qualify the clock using the LA_QUAL signal on P39 (POD2)
This qualification signal is asserted (1) when ADS#, RDY# or BRDY# is
asserted on the Am486 Microprocessor bus.
Thus cycles where valid address or data information is not transferred
can be filtered out when needed
Signals are arranged on the LA Headers to work with the HP Disassembler for the 16500 analyzer
BUFFERS AND LOGIC ANALYZER HEADERS FOR CPU SIGNALS
2.1
(C) Advanced Micro Devices, Inc. [phone]
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
426 Friday, December 04, 1998
Title
Size Document Number Rev
Date: Sheet of
VGD30
VGD28
VGD26
VGD24
VGD22
VGD20
VGD18
VGD16
VGD31
VGD29
VGD27
VGD25
VGD23
VGD21
VGD19
VGD17
GD25
GD18
GD3
GD23
GD26
GD29
GD9
GD6
GD24
GD21
GD1
GD31
GD7
GD13
GD11
GD4
GD12
GD5
GD27
GD22
GD15
GD10
GD20
GD14
GD2
GD30
GD0
GD8
GD19
GD17
GD16
GD28
VGD14
VGD12
VGD10
VGD8
VGD6
VGD4
VGD2
VGD0
VGD15
VGD13
VGD11
VGD9
VGD7
VGD5
VGD3
VGD1
VGD[0..31]
VGD31
VGD30
VGD29
VGD28
VGD27
VGD26
VGD25
VGD24
VGD23
VGD22
VGD21
VGD20
VGD19
VGD18
VGD17
VGD16
VGD15
VGD14
VGD13
VGD12
VGD11
VGD10
VGD9
VGD8
VGD7
VGD6
VGD5
VGD4
VGD3
VGD2
VGD1
GD [0..31]
VSRESET
VHITMJ
VPCHKJ
VSMIJ
VWB-WT#
VSMIACKJ
VFERRJ
VAHOLD
VNMI
VIGNNEJ
VPLOCK#
VGD0
VCACHE#
VSTPCLKJ
VINV
FE RRJ
WB-WT#
SMIACKJ
SMIJ
PCHKJ
GD[0..31]
IGNNEJ
AHOLD
NMI
STPCLKJ
HITMJ
CPURST
PCD_CACH
INV
PLOCK#
VCC
VCC
VCC
P47
HP CONN
3M:2520-6003UB
2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
1
CLK2
CLK1 D15
D14 D13
D12 D11
D10 D9
D8 D7
D6 D5
D4 D3
D2 D1
D0 GND
+5V
P36
HP CONN
3M:2520-6003UB
2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
1
CLK2
CLK1 D15
D14 D13
D12 D11
D10 D9
D8 D7
D6 D5
D4 D3
D2 D1
D0 GND
+5V
P38
HP CONN
3M:2520-6003UB
2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
1
CLK2
CLK1 D15
D14 D13
D12 D11
D10 D9
D8 D7
D6 D5
D4 D3
D2 D1
D0 GND
+5V
U26
74ABT16244
1
48
7
18
25
24
31
42
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
21
4
10
15
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
28
34
39
45
1OE#
2OE#
VCC
VCC
3OE#
4OE#
VCC
VCC
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
GND
GND
GND
GND
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
GND
GND
GND
GND
U28
74ABT16244
1
48
7
18
25
24
31
42
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
21
4
10
15
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
28
34
39
45
1OE#
2OE#
VCC
VCC
3OE#
4OE#
VCC
VCC
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
GND
GND
GND
GND
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
GND
GND
GND
GND
U47
74ABT16244
1
48
7
18
25
24
31
42
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
21
4
10
15
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
28
34
39
45
1OE#
2OE#
VCC
VCC
3OE#
4OE#
VCC
VCC
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
GND
GND
GND
GND
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
GND
GND
GND
GND