User`s manual

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Table of Contents
Page 1: COVER.SCH
Page 2: CPU.SCH
Page 6: M1489.SCH
Page 7: L2_CACHE.SCH
Page 8: SIMM_SKTS.SCH
Page 9: EIP_MEM1.SCH
Page 11: PCI_CONN.SCH
Page 12: PCI_VIS.SCH
Page 13: ENET1.SCH
Page 14: ENET2.SCH
Page 15: IDE.SCH
Page 16: M1487.SCH
Page 17: ROM_MISC.SCH
Page 18: CLOCK.SCH
Page 19: ISA_CONN.SCH
Page 4: CPU_VIS1.SCH
Page 3: CPU_POWER.SCH
Page 20: SUPER_I/O.SCH
Page 21: SERIAL_PARALLEL.SCH
Page 22: ISA_MEM1.SCH
Page 24: RTC_TIP.SCH
Page 23: ISA_MEM2.SCH
Page 10: EIP_MEM2.SCH
Page 25: KEYBOARD.SCH
Page 26: CPU_PINOUT.SCH
Original designRev 1.0:
Rev 1.1:
Rev 1.2:
Minor modifications after Design Review
Added External 8042 Style Keyboard Controller (SH24)
Removed Support for M1487 Internal KBC (SH15)
Removed Keyboard Interface From Clock Page (SH17)
Changed design name to Am486PCI C.D.P.
Rev 1.3: Added Extra Bypass Capacitors (SH5 & SH14 & SH15 & SH17)
Swapped Around Some Signals Within Resistor Networks (SH6 & SH20)
Renamed MCLK1 net to M_CLK1 (SH24)
Added 0-ohm resistor to make pin 10 & 11 pullup work (SH17)
Added Pin to HS1 for NetLister (SH3)
Fixed Error in 3.3V Regulator Circuit (SH12)
Rearranged Clock Nets to Facilitate Routing (SH17)
Changed Some Components to Standard Values
(50ohm to 49.9ohm, 1% on SH 13 and 40pF to 39pF,
5% on SH19)
Rev 1.4:
Page 5: CPU_VIS2.SCH
Note: Unless otherwise stated the capacitors are a 0805 package and 10% Tol.
Note: Unless otherwise stated the resistors are a 0805 package and 5% Tol.
Added jumpers to allow mulitple BIOS images in a single Flash ROM device
Removed 1 diode from VBAT generation circuit
Added new NMI generation circuit and spare ’F14 gates
Added jumper for external RESET# pushbutton
Fixed wiring error on crystal
Removed MCLK1 net (16MHz) and rewired MCLK2 to drive all 33MHz clock nets
Removed CLKCNTL signal from DOZE# pin of U17
Removed unneeded 0-ohm resistors from Super I/O chip
Fixed wiring error on crystal
Added ’ABT125 buffer to drive serial port LEDs
MACH device outputs changed for new ISA Flash support
Changed ISA Flash to 1MByte (512Kx16)
Removed unneeded logic from RTC interface
Added inverter to generate proper CS# for RTC chip
Fixed wiring error on crystal
Grounded U22-pin 22
Removed 1 unused OR gate for use on SH17
Switched mouse connector to verticle type
Changed ’F06 symbol to show o/c
SH17:
SH18:
SH20:
SH22:
SH23:
SH24:
SH25:
Am486 Microprocessor Development System With PCI Expansion and On-Board Am79C972 100MB/s Ethernet Controller
Note: Unless otherwise noted all logic operates off a 5V power supply
SH11:
SH16:
SH9:
SH15:
Changed SIP resistor packs to 10-pin (SH2, SH3, SH11, SH15, SH16, SH17, SH19, SH20 & SH21)
Changed 330ohm SIP Resistor Pack to 8-pin (SH19)
Added a 4K serial EEPROM for user parameters and mux. circuit to daisy chain it off the 1K device.
’972 E/net device loads its configuration from 1K SEEPROM.
CLKCNTL signal from M1487 used to select 1K or 4K SEEPROM.
Broke CPU Logic Analyzer Headers into 2 pages
Added PAL to gnerate CPU A0 and A1 and also generate a Logic Analyzer Qualify signal
Buffered BE[0..3], RDY#, BRDY#, and ADS# through the new PAL
Swapped R107 and R109; R109 is 49.9ohm, 1%
Fixed wiring error on crystal
Added 5 more 0.1uF bypass capacitors for new chips (’F14, ’ABT125, 22V10, ’F08, ’C66)
SH4 & 5:
Fixed wiring error on crystal
Fixed wiring error in generation of low-active reset signal RSTDRV#
Removed unused inverter (used on SH24)
Changed net on NMI pin to 1487NMI for use in new circuit
Changed R58 to be a populated component
Rev 2.0:
SH14:
Added diagram to correct Power Connector FootprintSH3:
SH13:
Added configuration information for PCI slots
Removed circuit to generate PCI PERR# to cause
M1487 to assert NMI to Am486 microprocessor
Added better explanation of EIP Flash memory operation
Rev 2.0 (continued):
Modified ROM jumpers to allow mulitple BIOS images in a single Flash ROM
device and support 256K or 512K BIOS for non-PC applications
Added XBUSCSJ signal to Mach device so it does not respond when Am486
fetches the reset vector at FFFF FFF0
SH17:
SH22:
Rev 2.1: Updated revision level and prototype warning on all sheets
SH14 &15 &20: Connected pins 1 and 2 on all LEDs for greater
purchasing/manufacturing flexibility
Am486 Microprocessor
PCI Customer
Development Platform
Am486 MICROPROCESSOR
PCI CUSTOMER DEVELOPMENT PLATFORM
2.1
(C) Advanced Micro Devices, Inc. [phone]
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
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26 Friday, December 04, 1998
COVER.SCH
Title
Size Document Number Rev
Date: Sheet of