User`s manual

Am486
®
Microprocessor PCI Customer Development Platform User’s Manual
2-34
Reset and Interrupt Switches and Headers
Three push-button switches are provided so the user can generate RESET, SMI,
and NMI events. In addition, a two-pin header is provided for the RESET signal
so that an external pushbutton switch can be attached. These switches and headers
are routed to the appropriate chipset signals as listed in Table 2-10.
Table 2-10. Switch Summary
Embedded BIOS software typically enters its debugging monitor when an NMI
event is generated. In addition to pressing the NMI switch, an NMI event can be
caused by a PCI-bus parity error, a DRAM parity error, or an ISA-bus IOCHCK
error.
Part Signal Description Location in
Figure 2-3
on Page 2-5
See App. B
Schematics
on:
SW1,
JP34
PWG Used to reset the system. N5, K23 Sheet 17
SW2 NMI Used to generate an NMI
event.
K6 Sheet 17
SW3 EXTSMI Used to generate an SMI
event.
H11 Sheet 17