User`s manual

Am486
®
Microprocessor PCI Customer Development Platform User’s Manual
2-26
Software that writes to the EIP Flash memory must also avoid any back-to-back
write cycles (including back-to-back non-burst cycles) to the EIP Flash memory
space. For reliable writes, always read or write a different DRAM bank (0, 1 or 2)
before and after writes to the EIP space. For example, read location 00000h, write
a value to Flash memory, and then read location 00000h again. (Simply running
the Flash programming software in the normal DRAM space does not ensure
reliable Flash programming, even though caching is disabled.)
Reading the EIP Flash memory does not entail any of the timing restrictions that
apply to writes. The microprocessor can read EIP Flash memory with any
combination of single-beat or burst read cycles.
The EIP Flash memory itself is organized in two banks. The base address of each
EIP bank depends on how much DRAM is installed in DRAM banks 0–2. The
board is shipped with 48 Mbytes installed, so by default the EIP first bank base
address is 3000000h (48 Mbytes + 1 byte), and the EIP second bank base address
is 3400000. See Figure 2-6 on page 2-24. Software can query the chipset’s DRAM
Configuration Registers (index 10h and 11h) to determine the size of banks 0–2.
See the chipset documentation for a description of these registers.
Each Flash device is configured in byte mode, with four devices in each EIP bank.
The CPU address signals are routed so that CPU address bit A2 is routed to bit A0
on the Flash devices, so the EIP space can only be addressed on even 4-byte (32-
bit double-word) boundaries. When writing to the devices’ control registers,
multiply the byte-mode register offset by four to generate the correct CPU address.
For example, if the bank base address is 3000000h, writing address 3002AA8h
asserts AAAh (2AA8h ÷ 4) on each Flash device’s address pins.