User`s manual

Am486
®
Microprocessor PCI Customer Development Platform
2-25
EIP Flash Memory (L21)
The PCI CDP includes 8 Mbytes of Flash memory for execute-in-place (EIP)
applications. The EIP Flash memory is implemented in the fourth bank (bank 3)
of the DRAM controller’s address space. This memory consists of eight 29F800B
top-sector boot block Flash memory devices (parts U61, U62, U63, U64, U65,
U66, U67, and U68), soldered to the board and organized as two 32-bit wide Flash
memory banks.
The EIP Flash memory is controlled by an AMD 22V10 PAL
®
device programmed
to act as a simple DRAM-to-Flash interface that makes the Flash memory appear
to the M1489 DRAM controller as a single bank of 32-bit-wide EDO DRAM.
The provided BIOS enables the EIP Flash memory and configures the other DRAM
banks accordingly. To enable the EIP Flash memory, the BIOS programs the
chipset’s DRAM Configuration Register 2 (index 11h, bits 4–7) so the fourth
DRAM bank is accessed as 2-Mbyte by 8 (11 row, 10 column) DRAM chips. The
DRAM-to-Flash interface uses CPU address bit A22 for Flash memory bank
switching (A22 is routed to DRAM address bit 8 in the selected configuration).
Because of timing requirements, it is also necessary to program the chipset’s
DRAM Configuration and Timing Control registers (index 1Ah and 1Bh) to disable
hidden refresh, disable RAS
-only refresh, select Fast access mode (not Fastest),
and select CAS
before RAS refresh. This affects all four DRAM banks.
The EIP Flash memory can be accessed only by the CPU (no PCI bus-master access
to the EIP Flash is allowed), and all accesses are 32 bits wide. During normal
operation, the EIP Flash memory can be read like other DRAM memory, but data
cannot be written directly. Instead, the Am29F800 devices are programmed using
the JDEC single-power-supply Flash standard command set. See the Am29F800
documentation for details. Software for using Flash memory is provided with the
PCI CDP. See the readme file on the diskette that came with your kit for information
about available utilities.
Software that writes to the EIP Flash memory must make sure that accesses to the
Flash memory are not cached. This can be done by disabling Level-1 and Level-2
memory caching, or by appropriate programming of the page tables if paging is
enabled in the microprocessor.