User`s manual

Am486
®
Microprocessor PCI Customer Development Platform User’s Manual
2-22
Figure 2-5. JP32 and JP33 Jumper Configuration (B14–C14)
By default, jumpers JP32 and JP33 are not connected, so ROM device pins A17
and A18 are tied High to address the 128-Kbyte BIOS range, E0000h–FFFFFh. If
these jumpers are changed to select ISA addressing for addresses
C0000h–DFFFFh, software must enable ROM addressing for this space via chipset
register index 12h, bits 2–1, and index 44h, bits 7–6.
For software compatibility, the boot ROM image appears from E0000h to FFFFFh
in the Am486 microprocessor’s lower 1-Mbyte address space. (This assumes that
a 128-Kbyte boot ROM is used.) At reset, however, the microprocessor is in a
special state that causes it to fetch its first instruction from FFFFFFF0h, at the top
of its extended memory range. To provide the first instruction, the boot ROM is
aliased to begin at FFFE0000h. One of the first instructions is typically a far jump,
which ends the special state and causes the microprocessor to continue execution
in the lower 1-Mbyte space.
Because boot ROM accesses are relatively slow, subsequent initialization code
typically copies the boot ROM contents into DRAM space and configures the
chipset’s Shadow Region Register to direct all boot ROM accesses to this shadow
image of the boot ROM.
JP32JP33
Boot ROM
ROM Pin
ISA Signal
(SA17 or SA18)
(A17 or A18)
5 V
ROM Jumper Locations Individual Jumper Schematic
12 312 3
(SA18) (SA17)
12 3