User`s manual

Am486
®
Microprocessor PCI Customer Development Platform
2-21
Table 2-7. SIMM Socket Population Chart
NOTE: 32- or 36-bit-wide memory can be used. However, 36-bit EDO SIMMs
are accessed as only 32 bits wide because the FINALi chipset does not support
EDO SIMMs’ 32-bit data plus 4-bit error correction code (ECC) format. Only
traditional byte-wide parity is supported.
Boot ROM (C16)
The PCI CDP provides a 0.5-inch wide 32-pin DIP socket (part U14) for an
initialization or BIOS ROM device. The boot ROM is implemented on the M1487
chip’s LinkBus.
The boot ROM socket is populated with a BIOS that allows the PCI CDP to boot
and run DOS, Windows, or a real-time operating system (RTOS) immediately.
The platform must always boot from the boot ROM because of chipset limitations.
The chipset does not allow booting from another source such as DRAM-bus, ISA-
bus, or PCI-bus memory.
The boot ROM address space size defaults to 128 Kbytes, using ROM device
address bits A0–A16, but the board design provides jumpers JP32 and JP33 (at
locations C14 and B14) for configuring the ROM device’s A17 and A18 address
signals. The jumpers allow these address bits to be left High, tied Low, or connected
to their corresponding ISA bus signal. This provides flexibility in addressing
various sized Flash memory or ROM devices. See Figure 2-5 on page 2-22
SIMM 0 SIMM 1 SIMM 2
Single Bank SIMM Single Bank SIMM Single Bank SIMM
Double Bank SIMM Single Bank SIMM —