User`s manual

Am486
®
Microprocessor PCI Customer Development Platform User’s Manual
2-20
Level-2 Cache Memory (K19–N19 and N11)
The PCI CDP includes an onboard 512-Kbyte, single-bank, direct-mapped, unified
Level-2 cache. This is the largest single-bank cache allowed by the chipset. The
cache tag and data static RAM (SRAM) devices are soldered onto the PCI CDP
board. A 10-ns tag SRAM device and 15-ns data SRAM devices are used to achieve
2-1-1-1 timing on reads and 2-2-2-2 on writes.
The tag SRAM is a single 32-K by 8-bit device, part U11, and the data SRAMs
are 128-K by 8-bit devices, parts U7, U8, U9, and U10.
Chipset registers allow the level-2 cache to be disabled or enabled. The level-2
cache can be configured for either write-back or write-through operation.
NOTE: The benefit of level-2 cache varies, depending on the software being used.
DRAM Main Memory (P7)
The PCI CDP comes with three standard, 5-V, 72-pin single inline memory module
(SIMM) sockets, populated with three 16-Mbyte, 60-ns, extended data out (EDO)
SIMMs.
The included SIMMs provide the largest and fastest DRAM configuration allowed
in this design. For customer designs, the SIMM configurations supported depend
upon the chipset and the initialization or BIOS code used to configure the chipset’s
registers. See the chipset documentation for information about detecting and
configuring DRAM. The BIOS provided will automatically detect the amount of
DRAM installed.
The chipset used in this design supports 2-, 4-, 8-, 16-, or 32-Mbyte SIMMS using
4- or 16-Mbit technology DRAM chips. Either fast page mode (FPM) or EDO
SIMMs can be used, and the sockets can be filled with a combination of FPM or
EDO SIMMs. All installed SIMMs must be run at the same speed, however.
The chipset allows either 1, 2, or 3 DRAM banks. Single- and double-bank SIMMs
can be combined as shown in Table 2-7 on page 2-21.