User`s manual

Am486
®
Microprocessor PCI Customer Development Platform
2-17
In addition to the logic analyzer headers, separate three-pin headers are provided
for each PCI device’s bus request and bus grant signals. These headers are listed
in Table 2-4:
In-Circuit Emulator Compatibility (M14, Q15–Q16)
The PCI CDP can be used with an in-circuit emulator that mates to the pin-grid-
array (PGA) zero-insertion-force (ZIF) socket in place of the Am486
microprocessor. To support emulators that use an Intel microprocessor, the
necessary CPU power-supply jumpers are provided so the board will work with
Intel 486 DX2 and DX4 chips. See “CPU Voltage Adjustment (Q15–Q16)” on
page 2-32.
When connecting an in-circuit emulator, risers might be required to allow proper
placement relative to the microprocessor socket and the ISA slots.
Hexadecimal Display (H23, J23)
The PCI CDP includes 2-digit hexadecimal displays for port 80h and port 680h
debugging messages. To change the display value, perform an 8-bit write to I/O
port 80h or 680h, respectively. The value written is latched by the display and
cannot be read back by software.
Table 2-4. PCI Bus Master Test Points
Part Signal Location in
Figure 2-3 on
Page 2-5
See App. B
Schematics
on:
JP29 PREQJ0
PGNTJ0
GND
I6 Sheet 12
JP30 PREQJ1
PGNTJ1
GND
K5 Sheet 12
JP31 PREQJ2
PGNTJ2
GND
E7 Sheet 12