User`s manual

Am486
®
Microprocessor PCI Customer Development Platform
2-15
Development Support
The PCI CDP includes the following facilities for development support:
•JTAG port
• CPU-bus and PCI-bus logic analyzer headers
• Port 80 and Port 680 hexadecimal displays
• TIP board interface
These features are described in the following paragraphs.
JTAG Ports (Q14 and D17)
The Am486 microprocessor provides an IEEE Standard 1149.1-1990 (JTAG)
compliant test access port and boundary-scan architecture. The JTAG port provides
a scan interface for testing the microprocessor in a production environment. The
microprocessor’s JTAG port is available on connector J35 at location Q14.
Do not attempt use the second JTAG port (part P48 at location D17). This port is
used at AMD to program the Vantis™ MACH
®
programmable logic device.
Reprogramming of the MACH device can cause improper system operation. The
MACH device controls the ISA Flash memory space and the Port 80h and 680h
hexadecimal displays. See “ISA Flash Memory (F20)” on page 2-23 and
“Hexadecimal Display (H23, J23)” on page 2-17.
Logic Analyzer Headers
The CPU interface signals are buffered and routed to headers for a logic analyzer.
The signals on the CPU bus logic analyzer headers are arranged to be compatible
with the disassembler for the HP 16500 Logic Analyzer, but any analyzer can be
used. Table 2-3 lists the available headers, their locations in Figure 2-3, and the
Appendix B schematics sheet on which they appear. Sheet 4 of the schematics
includes usage notes.