User`s manual

Am486
®
Microprocessor PCI Customer Development Platform Users Manual
2-12
All PCI bus signals are routed to logic analyzer headers. See “Development
Support” on page 2-15.
The M1487 ISA Bridge Controller (often called a southbridge chip) interfaces the
ISA bus to the PCI bus and provides standard, PC-compatible peripherals devices
common to desktop computers. The M1487 (Part U21 at location I13) provides
the following peripheral functions:
Two 82C59 interrupt controllers
One 82C54 programmable interval timer
Two 82C37 DMA controllers
A real-time clock (RTC) (optional on the CDP, see “Real-Time Clock (G17)”
on page 2-27)
External boot ROM decoding
The M1487’s integrated peripherals are configured for standard PC-AT
compatibility, so there is not much flexibility in assigning interrupts and DMA
channels.
The M1487 also contains the PCI bus arbiter, which allows three additional masters.
The PCI CDP board uses one master request/grant interface for the onboard
Am79C972 Ethernet controller. The other two master interfaces are routed to the
PCI expansion slots.
The M1489 and M1487 communicate with each other across their proprietary
LinkBus. The LinkBus has no separate pins, but instead uses the CPU address pins
A2 to A17. The LinkBus handles the RTC, keyboard controller, and boot ROM
transactions as well; this is why CPU address pins are routed to these devices in
the schematics. The chipset asserts the Am486 microprocessor’s AHOLD input to
three-state its address pins when the LinkBus is in use.