User`s manual

Am486
®
Microprocessor PCI Customer Development Platform
2-11
Core Logic Chipset (M8, I13, D15)
The PCI CDP uses the Acer Laboratories Inc. FINALi 486 chipset. The chipset
consists of two very-large-scale-integration (VLSI) devices that provide bus
interface and peripheral functions used in the system, plus an M5042 keyboard and
mouse controller. See “Keyboard (O1)” on page 2-31.
The M1489 Cache, Memory, and PCI Controller (often called a northbridge chip)
interfaces the Am486 microprocessor to the memory and PCI bus. The M1489
(part U5 at location M8) performs the following functions:
• Controls DRAM accesses and refresh cycles. See “DRAM Main Memory (P7)”
on page 2-20
• Provides a 33-MHz, PCI 2.0-compliant interface with 5-V signalling. See “PCI
Bus (I7)” on page 2-19
• Maintains Level-1 and Level-2 cache coherency for PCI-master-initiated
memory cycles. See “Level-2 Cache Memory (K19–N19 and N11)” on page
2-20
• Provides an IDE controller for a hard disk drive. See “IDE Hard Drive (L4 and
M4)” on page 2-31
The PCI CDP routes three PCI address signals via series resistors to the IDSEL
pins on the two PCI slots and the onboard Ethernet controller. The chipset asserts
one of these signals to configure each device according to the device number
written to the chipset’s configuration address register. Table 2-2 relates each device
to its device number and signal routing.
Table 2-2. PCI Configuration Addressing
PCI Device Device
Number
PCI Address
Signal
PCI ID Select
Signal
See App. B
schematics on:
Slot SLT1 Device 3 PAD19 PCIID1 Sheet 11
Slot SLT2 Device 4 PAD20 PCIID2 Sheet 11
Ethernet
Controller
Device 5 PAD21 PCIID3 Sheet 11, Sheet 13