User`s manual

Am486
®
Microprocessor PCI Customer Development Platform User’s Manual
2-10
Figure 2-4. Am486 Microprocessor Block Diagram
A31–A2
BE3
–BE0
ADS, W/R, D/C,
M/IO
, PCD, PWT,
RDY
, LOCK,
PLOCK
, BOFF,
A20M
, BREQ,
HOLD, HLDA,
RESET, INTR,
NMI, FERR
, UP,
IGNNE
, SMI,
SMIACT
, SRESET
VOLDET
V
CC
, V
SS
CLK
STPCLK
CLKMUL
Central and
Protection
Test Unit
Control
ROM
Instruction
Decode
Barrel Shifter
ALU
Register File
Segmentation
Unit
Descriptor
Registers
Paging Unit
Limit and
Attribute
PLA
Cache Unit
Prefetcher
Address
Drivers
Bus Control
Request
Sequencer
Data Bus
Transceivers
Burst Bus
Control
Bus Size
Control
Cache
Control
Parity
Generation
and Control
24
32
24
2
32
32
128
Decoded
Instruction
Path
Code
Stream
PCD, PWT
24
Displacement Bus
Bus Interface
D31–D0
BRDY
, BLAST
BS16, BS8
KEN, FLUSH,
AHOLD, CACHE
,
EADS
, INV,
WB/WT
, HITM
PCHK,
DP3
–DP0
TDI, TCK,
TDO, TMS
Power
Plane
Micro-instruction
Clock
Generator
Write
Buffers
4x32
Copyback
Buffers
4x32
Writeback
Buffers
4x32
Translation
Lookaside
Buffer
16-Kbyte
Cache
32-Byte
Code Queue
2x16 Bytes
JTAG
Clock
Interface
Physical
Address
Floating
Point
Unit
Floating
Point
Register
File
32-Bit Data Bus
32-Bit Linear Address
32-Bit Data Bus
Physical
Address