User`s manual

Am486
®
Microprocessor PCI Customer Development Platform Users Manual
2-8
Am486 Microprocessor (M14)
The PCI CDP includes an Am486 microprocessor in a 168-pin, pin-grid-array
package (part U25). The microprocessor is zero-insertion-force (ZIF) socketed and
a CPU fan heat sink is provided for cooling. For debugging and analysis, access
is provided to the Am486 microprocessor’s JTAG debugging port and to all of the
microprocessor signals, and support is provided for Intel-compatible in-circuit
emulators. See “Development Support” on page 2-15.
The Enhanced Am486DX Microprocessor Family boosts system performance by
incorporating a 16-Kbyte cache to the existing flexible clock control and enhanced
System Management mode (SMM) features of a 486 CPU. The Enhanced
Am486DX Microprocessor Family has the following characteristics:
Industry-standard write-back cache support
Frequent instructions execute in one clock
105.6-million bytes/second burst bus at 33 MHz
Flexible write-through and write-back address control
Advanced 0.35-µ CMOS-process technology
3.3-V or 3.45-V core with 5-V tolerant I/O
Dynamic data bus sizing for 8-, 16-, and 32-bit buses (the PCI CDP uses a 32-
bit data bus)
32-bit address bus
32-bit registers
Supports “soft reset” capability
16-Kbyte unified code and data cache
Four-way set-associative
Write-through or write-back policy (the PCI CDP uses write-back policy)
Floating-point unit
Paged, virtual memory management
Stop clock control for reduced power consumption
Industry-standard two-pin System Management Interrupt (SMI
) for power
management independent of processor operating mode and operating system