User`s manual

Am486
®
Microprocessor PCI Customer Development Platform User’s Manual
xiv
DRAM Main Memory
• 48 Mbyte of 60-ns EDO DRAM installed.
• Supports one, two, or three banks of 32- or 36-bit-wide DRAM using industry
standard 5-V 72-pin SIMMs. DRAM can be fast page mode (FPM) or extended
data out (EDO).
• Supports 1-, 4-, or 16-Mbit technology DRAMs.
• Three SIMM sockets. One or two banks per socket. Three banks DRAM
maximum.
• DRAM is accessible by CPU and PCI bus masters.
• L1/L2 cache snoop cycles are generated for PCI master memory accesses.
• Wait-state timing is configurable through chipset registers.
Boot ROM and Flash Memory
• Dip socket provided for one 8-bit-wide boot ROM, logically on the ISA bus.
• 1 Mbyte of 16-bit-wide Flash memory soldered to the board, logically on ISA
bus.
• 8-Mbyte Flash memory for execute-in-place (EIP) applications, located on the
memory bus in place of one DRAM bank. EIP Flash is implemented using an
AMD 22V10 PAL
®
device for glue logic.
Onboard L2 Cache
• 512-Kbyte cache size, configured as 32-bit-wide memory.
• Write-back or write-through protocol configurable through chipset registers.
• One 32-Kbyte x8 SRAM for cache tag space, soldered to board.
• Four 128-Kbyte x8 SRAMs for cache data space, soldered to board.
• 2-1-1-1 (read) and 2-2-2-2 (write) burst timing with 15-ns data and 10-ns tag
SRAMs.