Datasheet

Intel
®
Xeon
®
Processor 5500 Series Datasheet, Volume 1 21
Intel® Xeon® Processors 5500 Series Electrical Specifications
Notes:
1. When the “11111111” VID pattern is observed, or when the SKTOCC# pin is high, the voltage regulator
output should be disabled.
2. Shading denotes the expected VID range of the Intel Xeon Processor 5500 Series.
3. The VID range includes VID transitions that may be initiated by thermal events, Extended HALT state
transitions (see Section 7.2), higher C-States (see Section 7.2) or Enhanced Intel SpeedStep
®
Technology
transitions (see Section 7.5). The Extended HALT state must be enabled for the processor to
remain within its specifications
4. Once the VRM/EVRD is operating after power-up, if either the Output Enable signal is de-asserted or a
specific VID off code is received, the VRM/EVRD must turn off its output (the output should go to high
impedance) within 500 ms and latch off until power is cycled.
2.1.7.3.1 Power-On Configuration (POC) Logic
VID[7:0] signals also serve a second function. During power-up, Power-On
Configuration POC[7:0] functionality is multiplexed onto these signals via 1-5 kΩ pull-
up or pull down resistors located on the baseboard. These values provide voltage
regulator keying (VID[7]), inform the processor of the platforms power delivery
capabilities (MSID[2:0]), and program the gain applied to the ISENSE input
(CSC[2:0]). Table 2-3 maps VID signals to the corresponding POC functionality.
100111 0 00.63750
100111 0 10.63125
100111 1 00.62500
100111 1 10.61875
101000 0 00.61250
101000 0 10.60625
101000 1 00.60000
101000 1 10.59375
101001 0 00.58750
101001 0 10.58125
101001 1 00.57500
101001 1 10.56875
101010 0 00.56250
101010 0 10.55625
101010 1 00.55000
101010 1 10.54375
101011 0 00.53750
101011 0 10.53125
101011 1 00.52500
101011 1 10.51875
101100 0 00.51250
101100 0 10.50625
101100 1 00.50000
111111 1 0 OFF
111111 1 1 OFF
Table 2-2.Voltage Identification Definition (Sheet 5 of 5)
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 V
CC_MAX