Datasheet

Intel
®
Xeon
®
Processor 5500 Series Datasheet, Volume 1 131
Features
7 Features
7.1 Power-On Configuration (POC)
Several options can be configured by hardware. Power-On configuration (POC)
functionality is provided by strapping VID signals (see Table 2-3) or sampled on the
active-to-inactive transition of RESET#. For specifics on these options, please refer to
Table 7-1.
Please note that requests to execute Built-In Self Test (BIST) are not selected by
hardware, but rather passed across the Intel
®
QuickPath Interconnect link during
initialization.
Processors sample VID[2:0]/MSID[2:0] and VID[5:3]/CSC[2:0] around the asserting
edge VTTPWRGOOD.
Assertion of the PROCHOT# signal through RESET# de-assertion (also referred to as
Fault Resilient Boot (FRB)) will tri-state processor outputs. Figure 7-1 outlines timing
requirements when utilizing PROCHOT# as a power-on configuration option. In the
event an FRB is desired, PROCHOT# and RESET# should be asserted simultaneously.
Furthermore, once asserted, PROCHOT# should remain low long enough to meet the
Power-On Configuration Hold Time (PROCHOT#). Failure to do so may result in false
tri-state.
Table 7-1. Power On Configuration Signal Options
Configuration Option Signal Reference
Output tristate PROCHOT#
1
Notes:
1. Asserting this signal during RESET# de-assertion will select the corresponding option. Once selected, this
option cannot be changed except via another reset. The processor does not distinguish between a "warm"
reset and a "power-on" reset. Output tri-state via the PROCHOT# power-on configuration option is referred
to as Fault Resilient Boot (FRB).
Section 6.2.4
PECI ID ODT/PECI_ID#
2, 3
2. Latched when VTTPWRGOOD is asserted and all internal power good conditions are met.
Section 6.3.7.3
MSID VID[2:0]/MSID[2:0]
2, 3
3. See the signal definitions in Table 5-1 for the description of PECI_ID#, MSID, and CSC.
Table 2-3
CSC VID[5:3]/CSC[2:0]
2, 3
Table 2-3