Datasheet

Intel
®
Xeon
®
Processor 5500 Series Datasheet, Volume 1 119
Thermal Specifications
6.3.2.6.9 T-state Throttling Control Read / Write
PECI offers the ability to enable and configure ACPI T-state (core clock modulation)
throttling. ACPI T-state throttling forces all CPU cores into duty cycle clock modulation
where the core toggles between C0 (clocks on) and C1 (clocks off) states at the
specified duty cycle. This throttling reduces CPU performance to the duty cycle
specified and, more importantly, results in processor power reduction.
The Intel Xeon processor 5500 series software initiated T-state throttling and automatic
T-state throttling as part of the internal Thermal Monitor response mechanism (upon
TCC activation). The PECI T-state throttling control register read/write capability is
Table 6-21. Machine Check Bank Definitions
Bank Number Bank Index Meaning
0 0 MC0_CTL[31:0]
0 1 MC0_CTL[63:32]
0 2 MC0_STATUS[31:0]
0 3 MC0_STATUS[63:32]
0 4 MC0_ADDR[31:0]
0 5 MC0_ADDR[63:32]
0 6 MC0_MISC[31:0]
0 7 MC0_MISC[63:32]
1 0 MC1_CTL[31:0]
1 1 MC1_CTL[63:32]
1 2 MC1_STATUS[31:0]
1 3 MC1_STATUS[63:32]
1 4 MC1_ADDR[31:0]
1 5 MC1_ADDR[63:32]
1 6 MC1_MISC[31:0]
1 7 MC1_MISC[63:32]
6 0 MC6_CTL[31:0]
6 1 MC6_CTL[63:32]
6 2 MC6_STATUS[31:0]
6 3 MC6_STATUS[63:32]
6 4 MC6_ADDR[31:0]
6 5 MC6_ADDR[63:32]
6 6 MC6_MISC[31:0]
6 7 MC6_MISC[63:32]
8 0 MC8_CTL[31:0]
8 1 MC8_CTL[63:32]
8 2 MC8_STATUS[31:0]
8 3 MC8_STATUS[63:32]
8 4 MC8_ADDR[31:0]
8 5 MC8_ADDR[63:32]
8 6 MC8_MISC[31:0]
8 7 MC8_MISC[63:32]