Datasheet
Intel
®
Xeon
®
Processor 5500 Series Datasheet, Volume 1 113
Thermal Specifications
Description: Returns the data maintained in the PCI configuration space at the PCI
configuration address sent. The Read Length dictates the desired data return size. This
command supports byte, word, and dword responses as well as a completion code. All
command responses are prepended with a completion code that includes additional
pass/fail status information. Refer to Section 6.3.4.2 for details regarding completion
codes.
Note that the 4-byte PCI configuration address defined above is sent in standard PECI
ordering with LSB first and MSB last.
6.3.2.4.2 Supported Responses
The typical client response is a passing FCS, a passing Completion Code (CC) and valid
Data. Under some conditions, the client’s response will indicate a failure.
6.3.2.5 PCIConfigWr()
The PCIConfigWr() command gives sideband write access to the PCI configuration
space maintained in the processor. The exact listing of supported devices, functions is
defined below in Table 6-17. PECI originators may conduct a device/function/register
enumeration sweep of this space by issuing reads in the same manner that BIOS
would.
Figure 6-17. PCIConfigRd()
Byte #
Byte
Definition
0
Client Address
1
Write Length
0x05
2
Read Length
{0x02,0x03,0x05}
8
FCS
3
Cmd Code
0xc1
9
Completion
Code
10
Data 0 ...
8+RL
Data N
9+RL
FCS
4 5 6 7
LSB MSBPCI Configuration Address
Table 6-16. PCIConfigRd() Response Definition
Response Meaning
Abort FCS Illegal command formatting (mismatched RL/WL/Command Code)
CC: 0x40 Command passed, data is valid
CC: 0x80 Error causing a response timeout. Either due to a rare, internal timing condition or a
processor RESET or processor S1 state. Retry is appropriate outside of the RESET or
S1 states.