User manual

Appendix D Register-Level Programming
PC-DIO-96/PnP User Manual D-2 © National Instruments Corporation
counter uses. The configuration bits are defined in the Register
Description for the 82C53 section later in this appendix.
In addition to the 82C55A devices and the 82C53 device, there are two
registers that select which onboard signals are capable of generating
interrupts. There are two interrupt signals from each of the four 82C55A
devices and two interrupt signals from the 82C53 device. Individual
enable bits select which of these 10 signals can generate interrupts.
Also, a master enable signal determines whether the board can actually
send a request to the host computer. The configuration bits for these
registers are defined in the Register Description for the Interrupt
Control Registers section later in this appendix.
Register Map
The following table lists the address map for the PC-DIO-96/PnP.
Table D-1. PC-DIO-96/PnP Address Map
Register Name Offset Address
(Hex)
Size Type
82C55A Register Group
PPI A
PORTA Register 00 8-bit Read-and-write
PORTB Register 01 8-bit Read-and-write
PORTC Register 02 8-bit Read-and-write
CNFG Register 03 8-bit Write-only
PPI B
PORTA Register 04 8-bit Read-and-write
PORTB Register 05 8-bit Read-and-write
PORTC Register 06 8-bit Read-and-write
CNFG Register 07 8-bit Write-only