PC-DIO-96/PnP User Manual Digital I/O Board for ISA September 1996 Edition Part Number 320289C-01 © Copyright 1990, 1996 National Instruments Corporation. All Rights Reserved.
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Important Information Warranty The PC-DIO-96/PnP is warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
Table of Contents About This Manual Organization of This Manual ........................................................................................ ix Conventions Used in This Manual ............................................................................... x National Instruments Documentation ........................................................................... xii Related Documentation ................................................................................................
Table of Contents Digital I/O Signal Connections .....................................................................................3-7 Power Connections ........................................................................................................3-9 Digital I/O Power-up State Selection ............................................................................3-9 High DIO Power-up State ...............................................................................
Table of Contents Glossary Index Figures Figure 1-1. The Relationship between the Programming Environment, NI-DAQ, and Your Hardware .............................................................. 1-4 Figure 2-1. PC-DIO-96PnP Parts Locator Diagram ................................................ 2-1 Figure 3-1. Figure 3-2. Digital I/O Connector Pin Assignments ...............................................
Table of Contents Tables Table 3-1. Table 3-2. Port C Signal Assignments ....................................................................3-4 Timing Signal Descriptions ...................................................................3-13 Table D-1. Table D-2. Table D-3. PC-DIO-96/PnP Address Map ..............................................................D-2 Port C Set/Reset Control Words ............................................................D-6 Mode 0 I/O Configurations ..................
About This Manual This manual describes the mechanical and electrical aspects of the PC-DIO-96/PnP and contains information concerning its operation and programming. The PC-DIO-96PnP is a member of the National Instruments PC Series of I/O channel expansion boards for ISA computers. These boards are designed for high-performance data acquisition and control for applications in laboratory testing, production testing, and industrial process monitoring and control.
About This Manual programmable peripheral interface. This interface is used on the PC-DIO-96/PnP board. • Appendix C, OKI 82C53 Data Sheet, contains the manufacturer data sheet for the OKI 82C53 integrated circuit (OKI Semiconductor). This circuit is used on the PC-DIO-96/PnP board. • Appendix D, Register-Level Programming, describes in detail the address and function of each of the PC-DIO-96/PnP control and status registers.
About This Manual monospace Text in this font denotes text or characters that are to be literally input from the keyboard, sections of code, programming examples, and syntax examples. This font is also used for the proper names of disk drives, paths, directories, programs, subprograms, subroutines, device names, functions, operations, variables, filenames, and extensions, and for statements and comments taken from program code.
About This Manual National Instruments Documentation The PC-DIO-96/PnP User Manual is one piece of the documentation set for your data acquisition (DAQ) system. You could have any of several types of manuals, depending on the hardware and software in your system. Use the different types of manuals you have as follows: PC-DIO-96/PnP User Manual • Getting Started with SCXI—If you are using SCXI, this is the first manual you should read.
About This Manual Related Documentation If you are a register-level programmer, the following documents contain information that you may find helpful as you read this manual: • Your computer technical reference manual • Plug and Play ISA Specification Customer Communication National Instruments wants to receive your comments on our products and manuals. We are interested in the applications you develop with our products, and we want to help if you have problems with them.
Chapter 1 Introduction This chapter describes the PC-DIO-96/PnP; lists what you need to get started; describes software programming choices, optional equipment, and custom cables; and explains how to unpack the PC-DIO-96/PnP. About the PC-DIO-96/PnP Thank you for purchasing the National Instruments PC-DIO-96/PnP. PnP refers to the Plug and Play technology used in this board. See the Conventions Used in this Manual section in About This Manual for an explanation.
Chapter 1 Introduction Note: – Macintosh II with a National Instruments NB-DIO-24, NB-DIO-32F, or PCI-DIO-96 – Any other computer with an 8-bit or 16-bit parallel interface • Centronics-compatible printers and plotters • Panel meters • Instruments and test equipment with BCD readouts and/or controls • Optically isolated, solid-state relays and I/O module mounting racks The PC-DIO-96/PnP cannot sink sufficient current to drive the SSR-OAC-5 and SSR-OAC-5A output modules.
Chapter 1 Introduction Software Programming Choices There are several options to choose from when programming your National Instruments DAQ and SCXI hardware. You can use LabVIEW, LabWindows/CVI, NI-DAQ, or register-level programming. NI-DAQ version 4.6.1 or earlier supports LabWindows for DOS. LabVIEW and LabWindows/CVI Application Software LabVIEW and LabWindows/CVI are innovative program development software packages for data acquisition and control applications.
Chapter 1 Introduction digital I/O, counter/timer operations, SCXI, RTSI, self-calibration, messaging, and acquiring data to extended memory. NI-DAQ has both high-level DAQ I/O functions for maximum ease of use and low-level DAQ I/O functions for maximum flexibility and performance. Examples of high-level functions are streaming data to disk or acquiring a certain number of data points. An example of a lowlevel function is writing directly to registers on the DAQ device.
Chapter 1 Introduction Register-Level Programming The final option for programming any National Instruments DAQ hardware is to write register-level software. Writing register-level programming software can be very time-consuming and inefficient, and is not recommended for most users. Even if you are an experienced register-level programmer, consider using NI-DAQ, LabVIEW, or LabWindows/CVI to program your National Instruments DAQ hardware.
Chapter 1 Introduction 24-channel I/O module mounting racks (such as those manufactured by Opto 22 and Gordos). The CB-100 cable termination accessory is available from National Instruments for use with the PC-DIO-96/PnP board. This kit includes two 50-conductor, flat-ribbon cables and a connector block. You can attach signal input and output wires to screw terminals on the connector block and therefore connect signals to the PC-DIO-96/PnP I/O connector.
Chapter 1 Introduction Recommended manufacturers and the appropriate part numbers for the standard ribbon cable (50-conductor, 28 AWG, stranded) that can be used with both the 100-pin and the 50-pin connectors are: • Electronic Products Division/3M (part number 3365/50) • T&B/Ansley Corporation (part number 171-50) Unpacking Your PC-DIO-96/PnP board is shipped in an antistatic package to prevent electrostatic damage to the board. Electrostatic discharge can damage several components on the board.
Chapter Installation and Configuration 2 This chapter describes how to install and configure the PC-DIO-96PnP board. Installation Note: You should install your driver software before installing your hardware. Refer to your NI-DAQ release notes for software installation instructions. 1 2 3 1 Serial Number 2 W1 3 F1 Figure 2-1.
Chapter 2 Installation and Configuration Note: The PC-DIO-96PnP uses 100 kΩ resistors for polarity selection at powerup. These signals are pulled up to VCC (+5 VDC, factory default) or pulled down to GND by selection of jumper W1. The location of W1 is shown in Figure 2-1. For more information, see the Digital I/O Power-up State Selection section in Chapter 3, Signal Connections. You can install the PC-DIO-96PnP in any available expansion slot in your computer.
Chapter 2 Installation and Configuration Hardware Configuration Plug and Play The PC-DIO-96PnP is fully compatible with the industry-standard Intel/Microsoft Plug and Play Specification. A Plug and Play system arbitrates and assigns resources through software, freeing you from manually setting switches and jumpers. These resources include the board base I/O address and interrupt channels.
Chapter 3 Signal Connections This chapter includes timing specifications and signal connection instructions for the PC-DIO-96/PnP I/O connector. Warning: Connections that exceed any of the maximum ratings of input or output signals on the PC-DIO-96/PnP can damage the board and the computer. The description of each signal in this section includes information about maximum input ratings. National Instruments is NOT liable for any damages resulting from any such signal connections.
Chapter 3 Signal Connections APC7 BPC7 APC6 BPC6 APC5 BPC5 APC4 BPC4 APC3 BPC3 APC2 BPC2 APC1 BPC1 APC0 BPC0 APB7 BPB7 APB6 BPB6 APB5 BPB5 APB4 BPB4 APB3 BPB3 APB2 BPB2 APB1 BPB1 APB0 BPB0 APA7 BPA7 APA6 BPA6 APA5 BPA5 APA4 BPA4 APA3 BPA3 APA2 BPA2 APA1 BPA1 APA0 BPA0 +5 V GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Chapter 3 Signal Connections I/O Connector Signal Connection Descriptions Pin Signal Name Description 1, 3, 5, 7, 9, 11, 13, 15 APC<7..0> Bidirectional Data Lines for Port C of PPI A—APC7 is the MSB, APC0 the LSB. 17, 19, 21, 23, 25, 27, 29, 31 APB<7..0> Bidirectional Data Lines for Port B of PPI A—APB7 is the MSB, APB0 the LSB. 33, 35, 37, 39, 41, 43, 45, 47 APA<7..0> Bidirectional Data Lines for Port A of PPI A—APA7 is the MSB, APA0 the LSB. 2, 4, 6, 8, 10, 12, 14, 16 BPC<7..
Chapter 3 Signal Connections Port C Pin Assignments The signals assigned to port C depend on the mode in which the 82C55A is programmed. In mode 0, port C is considered as two 4-bit I/O ports. In modes 1 and 2, port C is used for status and handshaking signals with zero, two, or three lines available for general-purpose input/output. The following table summarizes the signal assignments of port C for each programmable mode. Consult Appendix D, RegisterLevel Programming, for programming information.
Chapter 3 APC7 1 2 BPC7 APC6 3 4 BPC6 APC5 5 6 BPC5 APC4 7 8 BPC4 APC3 9 10 BPC3 APC2 11 12 BPC2 APC1 13 14 BPC1 APC0 15 16 BPC0 APB7 17 18 BPB7 APB6 19 20 BPB6 APB5 21 22 BPB5 APB4 23 24 BPB4 APB3 25 26 BPB3 APB2 27 28 BPB2 APB1 29 30 BPB1 APB0 31 32 BPB0 APA7 33 34 BPA7 APA6 35 36 BPA6 APA5 37 38 BPA5 APA4 39 40 BPA4 APA3 41 42 BPA3 APA2 43 44 BPA2 APA1 45 46 BPA1 APA0 47 48 BPA0 +5 V 49 50 GND Signal Connections Figure 3-2.
Chapter 3 Signal Connections CPC7 1 2 DPC7 CPC6 3 4 DPC6 CPC5 5 6 DPC5 CPC4 7 8 DPC4 CPC3 9 10 DPC3 CPC2 11 12 DPC2 CPC1 13 14 DPC1 CPC0 15 16 DPC0 CPB7 17 18 DPB7 CPB6 19 20 DPB6 CPB5 21 22 DPB5 CPB4 23 24 DPB4 CPB3 25 26 DPB3 CPB2 27 28 DPB2 CPB1 29 30 DPB1 CPB0 31 32 DPB0 CPA7 33 34 DPA7 CPA6 35 36 DPA6 CPA5 37 38 DPA5 CPA4 39 40 DPA4 CPA3 41 42 DPA3 CPA2 43 44 DPA2 CPA1 45 46 DPA1 CPA0 47 48 DPA0 +5 V 49 50 GND Figure 3-3.
Chapter 3 Signal Connections Digital I/O Signal Connections Pins 1 through 48 and pins 51 through 98 of the I/O connector are digital I/O signal pins. The following specifications and ratings apply to the digital I/O lines. Absolute maximum voltage rating -0.5 to +5.5 V with respect to GND Digital input specifications (referenced to GND): Input logic high voltage 2.2 V min 5.3 V max Input logic low voltage -0.3 V min 0.8 V max Maximum input current (0 < Vin < 5 V) -1.0 µA min 1.
Chapter 3 Signal Connections +5 V +5 V LED Jumper Selectable (W1) 100 kΩ 100 kΩ 100 kΩ 100 kΩ 41 PPI A Port A APA<3..0> 43 45 47 100 kΩ 100 kΩ 100 kΩ 100 kΩ 67 69 TTL Signal PPI C Port B CPB<7..4> 71 73 +5 V Switch * 50, 100 GND I/O Connector PC-DIO-96/PnP * Complex switch circuitry is not shown in order to simplify the figure. Figure 3-4. Digital I/O Connections In Figure 3-4, PPI A, port A is configured for digital output, and PPI C, port B is configured for digital input.
Chapter 3 Signal Connections Power Connections Pins 49 and 99 of the I/O connector are connected to the +5 V supply from the PC power supply. These pins are referenced to GND and can be used to power external digital circuitry. This +5 V supply has a 1 A protection fuse in series. This fuse is self-resetting. Simply remove the circuit causing the heavy current load and the fuse will reset itself. For more information on these output pins, see Output Signals in Appendix A, Specifications. 0.
Chapter 3 Signal Connections PC-DIO-96/PnP +5 V 100 kΩ 82C55 Digital I/O Line RL GND Figure 3-5. DIO Channel Configured for High DIO Power-up State with External Load Example: At power up, the board is configured for input and, by default, all DIO lines are high. To pull one channel low, follow these steps: 1. Install a load (RL). Remember that the smaller the resistance, the greater the current consumption and the lower the voltage (V). 2.
Chapter 3 Signal Connections Low DIO Power-up State If you select pulled-low mode, each DIO line will be pulled to GND (0 VDC) using a 100 kΩ resistor. If you want to pull a specific line high, connect a pull-up resistor that will give you a minimum of 2.8 VDC. The DIO lines are capable of sinking a maximum of 2.5 mA at 0.4 V in the low state. Use the largest possible resistance value so that you do not to use more current than necessary to perform the pull-up task.
Chapter 3 Signal Connections Example: At power up, the board is configured for input and jumper W1 is set in the low DIO power-up state, which means all DIO lines are pulled low. If you want to pull one channel high, follow these steps: 1. Install a load (RL). Remember that the smaller the resistance, the greater the current consumption and the lower the voltage (V). 2. Using the following formula, calculate the largest possible load to maintain a logic high level of 2.
Chapter 3 Table 3-2. Name Signal Connections Timing Signal Descriptions Type Description STB* Input Strobe Input—A low signal on this handshaking line loads data into the input latch. IBF Output Input Buffer Full—A high signal on this handshaking line indicates that data has been loaded into the input latch. This is an input acknowledge signal. ACK* Input Acknowledge Input—A low signal on this handshaking line indicates that the data written to the port has been accepted.
Chapter 3 Signal Connections Mode 1 Input Timing The following figure illustrates the timing specifications for an input transfer in mode 1. T1 T2 T4 STB* T7 IBF T6 INTR RD* T3 T5 DATA Name Description T1 STB* pulse width T2 Minimum Maximum 100 – STB* = 0 to IBF = 1 – 150 T3 Data before STB* = 1 20 – T4 STB* = 1 to INTR = 1 – 150 T5 Data after STB* = 1 50 – T6 RD* = 0 to INTR = 0 – 200 T7 RD* = 1 to IBF = 0 – 150 All timing values are in nanoseconds.
Chapter 3 Signal Connections Mode 1 Output Timing The following figure illustrates the timing specifications for an output transfer in mode 1. T3 WR* T4 OBF* T1 T6 INTR T5 ACK* DATA T2 Name Description Minimum Maximum T1 WR* = 0 to INTR = 0 – 250 T2 WR* = 1 to output – 200 T3 WR* = 1 to OBF* = 0 – 150 T4 ACK* = 0 to OBF* = 1 – 150 T5 ACK* pulse width 100 – T6 ACK* = 1 to INTR = 1 – 150 All timing values are in nanoseconds.
Chapter 3 Signal Connections Mode 2 Bidirectional Timing The following figure illustrates the timing specifications for bidirectional transfers in mode 2.
Chapter 4 Theory of Operation This chapter contains a functional overview of the PC-DIO-96PnP board and explains the operation of each functional unit making up the PC-DIO-96PnP. The block diagram in Figure 4-1 illustrates the key functional components of the PC-DIO-96PnP board.
Chapter 4 Theory of Operation The PC I/O channel consists of an address bus, a data bus, interrupt lines, and several control and support signals. Data Transceivers The data transceivers control the sending and receiving of data to and from the PC I/O channel. PC I/O Channel Control Circuitry The I/O channel control circuitry monitors and transmits the PC I/O channel control and support signals.
Chapter 4 Theory of Operation The 82C53 device has two of its three counter output signals connected to the interrupt circuitry. Any of these 10 signals can interrupt the host computer if the interrupt circuitry is enabled and the corresponding enable bit is set (see Appendix D, Register-Level Programming, for more information).
Chapter 4 Theory of Operation Digital I/O Connector All digital I/O is transmitted through a standard, 100-pin, male connector. Pins 49 and 99 are connected to +5 V through a protection fuse (F1). See Figure 2-1 in Chapter 2, Installation and Configuration, for its location. This +5 V supply is often required to operate I/O module mounting racks. Pins 50 and 100 are connected to ground.
Appendix A Specifications This appendix lists the specifications of the PC-DIO-96/PnP. These specifications are typical at 25° C, unless otherwise stated. The operating temperature range is 0° to 70° C. Digital I/O Number of channels ...........................96 I/O Compatibility .....................................TTL Absolute max voltage rating ..............-0.5 to +5.5 V with respect to GND Handshaking ......................................Requires 1 port Power-on state ...........................
Appendix A Specifications Output signals Pin 49 (at +5 V) .......................... 0.5 A max Pin 99 (at +5 V) .......................... 0.5 A max Note: The total combined current output from pins 49 and 99 may be limited by the available current from your computer power supply. To determine the available current, subtract the maximum power consumption of the board from the maximum current per slot. The difference, if less than 1 A, is the maximum combined current available to pins 49 and 99.
Appendix OKI 82C55A Data Sheet B This appendix contains the manufacturer data sheet for the OKI 82C55A* (OKI Semiconductor) CMOS programmable peripheral interface. This interface is used on the PC-DIO-96/PnP board. * © National Instruments Corporation Copyright © OKI Semiconductor 1993. Reprinted with permission of copyright owner. All rights reserved. OKI Semiconductor Data Book Microprocessor, Seventh Edition, March 1993.
Appendix OKI 82C53 Data Sheet C This appendix contains the manufacturer data sheet for the OKI 82C53* integrated circuit (OKI Semiconductor). This circuit is used on the PC-DIO-96/PnP board. * © National Instruments Corporation Copyright © OKI Semiconductor 1995. Reprinted with permission of copyright owner. All rights reserved. OKI Semiconductor Data Book Microprocessor, Eighth Edition, January 1995.
Appendix Register-Level Programming D This appendix describes in detail the address and function of each of the PC-DIO-96/PnP control and status registers. This appendix also includes important information about register-level programming on the PC-DIO-96/PnP along with program examples written in C and assembly language. Note: If you plan to use a programming software package such as LabWindows/CVI or NI-DAQ with your PC-DIO-96/PnP board, you need not read this appendix.
Appendix D Register-Level Programming counter uses. The configuration bits are defined in the Register Description for the 82C53 section later in this appendix. In addition to the 82C55A devices and the 82C53 device, there are two registers that select which onboard signals are capable of generating interrupts. There are two interrupt signals from each of the four 82C55A devices and two interrupt signals from the 82C53 device.
Appendix D Table D-1.
Appendix D Register-Level Programming Register Descriptions The register descriptions for the devices on the PC-DIO-96/PnP, including the 82C55A, the 82C53, and each of the interrupt control registers, are given on the pages that follow. Register Description for the 82C55A Figure D-1 shows the two control word formats used to completely program the 82C55A. The control word flag determines which control word format is being programmed.
Appendix D Group A D7 D6 D5 Register-Level Programming Group B D4 D3 D2 D1 D0 Control Word Flag Port C (low nibble) 1 = input 0 = output 1 = mode set Mode Selection 00 = mode 0 01 = mode 1 1X = mode 2 Port B 1 = input 0 = output Mode Selection 0 = mode 0 1 = mode 1 Port A 1 = input 0 = output Port C (high nibble) 1 = input 0 = output a.
Appendix D Register-Level Programming Table D-2 shows the control words for setting or resetting each bit in port C. Notice that bit 7 of the control word is cleared when programming the set/reset option for the bits of port C. Table D-2.
Appendix D D7 D6 D5 D4 D3 D2 D1 Register-Level Programming D0 BCD 1 = count in BCD 0 = count in binary Counter Select 00 = counter 0 01 = counter 1 10 = counter 2 11 = illegal Access Mode 00 = latch counter value 01 = access LSB only 10 = access MSB only 11 = access LSB, then MSB Mode Select 000 = mode 0 001 = mode 1 010 = mode 2 011 = mode 3 100 = mode 4 101 = mode 5 110 = mode 2 111 = mode 3 Figure D-2.
Appendix D Register-Level Programming Interrupt Control Register 1 D7 D6 D5 D4 D3 D2 D1 D0 DIRQ1 DIRQ0 CIRQ1 CIRQ0 BIRQ1 BIRQ0 AIRQ1 AIRQ0 Bit Name Description 7 DIRQ1 PPI D Interrupt Request for Port B—If this bit and the INTEN bit in Interrupt Control Register 2 are both set, PPI D sends an interrupt, INTRB, to the host computer. If this bit is cleared, PPI D does not send the interrupt INTRB to the host computer, regardless of the setting of INTEN.
Appendix D Register-Level Programming Bit Name Description (Continued) 2 BIRQ0 PPI B Interrupt Request for Port A—If this bit and the INTEN bit in Interrupt Control Register 2 are both set, PPI B sends an interrupt, INTRA, to the host computer. If this bit is cleared, PPI B does not send the interrupt INTRA to the host computer, regardless of the setting of INTEN.
Appendix D Register-Level Programming Interrupt Control Register 2 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X INTEN CTRIRQ CTR1 Bit Name Description 7–3 X Don’t Care Bit. 2 INTEN Global Interrupt Enable Bit—If this bit is set, the PC-DIO-96/PnP can interrupt the host computer. If this bit is cleared, the PnP version of this board cannot interrupt the host computer.
Appendix D Register-Level Programming Programming Considerations for the 82C55A Modes of Operation for the 82C55A The three basic modes of operation for the 82C55A are as follows: • Mode 0—Basic I/O • Mode 1—Strobed I/O • Mode 2—Bidirectional bus The 82C55A also has a single bit set/reset feature for port C, which is programmed by the 8-bit control word. For additional information, refer to Appendix B, OKI 82C55A Data Sheet.
Appendix D Register-Level Programming Mode 2 This mode can be used for communication over a bidirectional 8-bit bus. Handshaking signals are used in a manner similar to mode 1. Mode 2 is available for use in group A only (port A and the upper nibble of port C). Other features of this mode include the following: • One 8-bit bidirectional port (port A) and a 5-bit control/status port (port C). • Latched inputs and outputs. • Interrupt generation and enable/disable functions.
Appendix D Table D-3.
Appendix D Register-Level Programming /* EXAMPLE 1*/ outp(cnfg,0x80); outp(porta,0x12); outp(portb,0x34); outp(portc,0x56); /* /* /* /* Ports Write Write Write A, B, and C are data to port A. data to port B. data to port C. outputs. */ */ */ */ /* /* /* /* Port A is input; ports B and C are outputs. */ Write data to port B. */ Write data to port C. */ Read data from port A.
Appendix D Register-Level Programming D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1/0 X X X Port C bits PC6 and PC7 1 = input 0 = output The control word written to the CNFG Register to configure port B for input in mode 1 is shown as follows. Notice that port B does not have extra input or output lines from port C. D7 D6 D5 D4 D3 D2 D1 D0 1 X X X X 1 1 X During a mode 1 data read transfer, the status of the handshaking lines and interrupt signals can be obtained by reading port C.
Appendix D Register-Level Programming Bit Name Description (Continued) 2 INTEB Interrupt Enable Bit for Port B—Setting this bit enables interrupts from port B of the 82C55A. This bit is controlled by setting/resetting PC2. 1 IBFB Input Buffer for Port B—A high setting indicates that data has been loaded into the input latch for port B. 0 INTRB Interrupt Request Status for Port B—When INTEB and IBFB are high, this bit is high, indicating that an interrupt request is pending for port B.
Appendix D Register-Level Programming unsigned int porta, portb, portc, cnfg; char valread; /* Variable to store data read from a port */ /* Calculate register addresses */ porta portb portc cnfg = = = = BASE_ADDRESS BASE_ADDRESS BASE_ADDRESS BASE_ADDRESS + + + + APORTAoffset; APORTBoffset; APORTCoffset; ACNFGoffset; /* EXAMPLE 1–port A input */ outp(cnfg,0xB0); while (!(inp(portc) & 0x20)); /* Port A is an input in mode 1.
Appendix D Register-Level Programming D7 D6 D5 D4 D3 D2 D1 D0 1 X X X X 1 0 X During a mode 1 data write transfer, the status of the handshaking lines and interrupt signals can be obtained by reading port C. Notice that the bit definitions are different for a write and a read transfer.
Appendix D Register-Level Programming At the digital I/O connector, port C has the following pin assignments when in mode 1 output. Notice that the status of ACKA* and the status of ACKB* are not included when port C is read. Group A Group B PC7 OBFA* PC6 ACKA* PC5 I/O PC4 I/O PC3 INTRA PC2 ACKB* PC1 OBFB* PC0 INTRB Figure D-4.
Appendix D Register-Level Programming /* EXAMPLE 1–port A output */ outp(cnfg,0xA0); while (!(inp(portc) & 0x80)); /* Port A is an output in mode 1.*/ /* Wait until OBFA* is set, indicating that the data last written to port A has been read.*/ /* Write data to port A. */ outp(porta,0x12); /* EXAMPLE 2–port B output */ outp(cnfg,0x84); while (!(inp(portc) & 0x02)); /* Port B is an output in mode 1.*/ /* Wait until OBFB* is set, indicating that the data last written to port B has been read.
Appendix D Register-Level Programming Mode 2—Bidirectional Bus Mode 2 has an 8-bit bus that can transfer both input and output data without changing the configuration. The data transfers are synchronized with handshaking lines in port C. This mode uses only port A; however, port B can be used in either mode 0 or mode 1 while port A is configured for mode 2. The control word written to the CNFG Register to configure port A as a bidirectional data bus in mode 2 is shown as follows.
Appendix D Register-Level Programming Port C status-word bit definitions for bidirectional data path (port A only): D7 D6 D5 D4 D3 D2 D1 D0 OBFA* INTE1 IBFA INTE2 INTRA I/O I/O I/O Bit Name Description 7 OBFA* Output Buffer for Port A—A low setting indicates that the CPU has written data to port A. 6 INTE1 Interrupt Enable Bit for Port A Output Interrupts— Setting this bit enables output interrupts from port A of the 82C55A. This bit is controlled by setting/resetting PC6.
Appendix D Register-Level Programming At the digital I/O connector, port C has the following pin assignments when in mode 2. Notice that the status of STBA* and the status of ACKA* are not included in the port C status word.
Appendix D /* Register-Level Programming Calculate register addresses */ porta portb portc cnfg = = = = BASE_ADDRESS BASE_ADDRESS BASE_ADDRESS BASE_ADDRESS + + + + APORTAoffset; APORTBoffset; APORTCoffset; ACNFGoffset; /* EXAMPLE 1*/ outp(cnfg,0xC0); while (!(inp(portc) & 0x80)); /* Port A is in mode 2. */ /* Wait until OBFA* is set, indicating that the data last written to port A has been read. */ /* Write the data to port A.
Appendix D #define ACNFGoffset #define IREG1offset #define IREG2offset 0x03 0x14 0x15 Register-Level Programming /* Offset for PPI A, CNFG */ /* Offset for Interrupt Reg. 1 */ /* Offset for Interrupt Reg.
Appendix D Register-Level Programming /* EXAMPLE 5–Set up interrupts for mode 2 output transfers. Enable the appropriate interrupt bits. */ outp(cnfg,0xC0); outp(cnfg,0x0D); outp(ireg1,0x01); outp(ireg2,0x04); /* /* /* /* Mode 2 output. */ Set PC6 to enable interrupts from 82C55A. */ Set AIRQ0 to enable PPI A, port A interrupts. */ Set INTEN bit. */ /* EXAMPLE 6–Set up interrupts for mode 2 input transfers. Enable the appropriate interrupt bits.
Appendix D Register-Level Programming Interrupt Programming Example for the 82C53 An in-depth example of handling interrupts generated by the 82C53 is presented as follows. The main program is presented in C, while sample interrupt routines are presented in assembly language.
Appendix D Register-Level Programming /* Now write out the counter load values for the selected counters.
Appendix D Register-Level Programming decrementing all references to the base page register, bp, by two in install_isr() and remove_isr() only. Do not modify isr_handler().
Appendix D _TEXT ; ; ; ; ; ; ; ; ; Register-Level Programming segment word public 'CODE' assume cs:_TEXT, ss:_TEXT, ds:_DATA install_isr bp reg ret addr ofs ret addr seg level isr_block ofs isr_block seg _install_isr at at at at at at [bp+0] [bp+2] [bp+4] [bp+6] [bp+8] [bp+10] proc cli push mov push push push push push push mov mov far bp bp,sp ax bx cx dx ds es ax,seg _DATA ds,ax ; save the pointer for the isr_block structure--used in isr_handler mov ax,[bp+8] ; Get ofs into ax mov word ptr isr
Appendix D Register-Level Programming slave: add mov al,068h slave_ack,1 ; Offset for slave vector list ; Flag for slave channel push mov int pop mov mov cmp jne cmp je ax ; Save vector number for later ah,35h ; Get current vector 21h ; Get previous int_addr in es:bx ax ; Restore vector number cx,cs ; Prep to compare current/new vectors dx,es dx,cx ; See if vector is already there short ii_0 bx,offset _isr_handler short ii_exit ; Vector already installed--exit mov mov mov push mov mov mov int pop ve
Appendix D Register-Level Programming and out mov al,bh masks,al int_mask,cx ; Enable interrupts for selected level ; Save the previous value of the mask ; restore saved registers ii_exit: pop pop pop pop pop pop pop sti ret _install_isr ; ; ; ; ; ; es ds dx cx bx ax bp endp remove_isr bp reg ret addr ofs ret addr seg _remove_isr proc cli push push push push push push mov mov PC-DIO-96/PnP User Manual at [bp+0] at [bp+2] at [bp+4] far ax bx cx dx ds es ax,seg _DATA ds,ax D-32 © National Inst
Appendix D Register-Level Programming ; see if our vector is installed--if not, do not remove the vector cmp jz mov mov int mov mov cmp jne cmp jne vect_num,0 ; See if vect_num was ever set short ri_exit ; Our vector never installed--exit al,vect_num ; Get vector number ah,35h ; Get current vector from DOS 21h ; Get previous int_addr in es:bx cx,cs ; Prep to compare old/current vectors dx,es dx,cx ; See if our vector is already there short ri_exit ; Different vector segment--exit bx,offset _isr_handler s
Appendix D Register-Level Programming ; restore saved registers ri_exit: pop pop pop pop pop pop sti ret _remove_isr endp es ds dx cx bx ax ; isr_handler ; _isr_handler proc cli push push far ax ds ; service interrupt ; Your code here...
Appendix D Register-Level Programming ; acknowledge the interrupt ih_0: mov mov mov cmp je out jmp ax,seg _DATA ds,ax al,eoi slave_ack,0 short ih_1 acks,al $+2 out ackm,al ; Signify end of interrupt ; See if we need to acknowledge slave ; Jump if not ; Send slave acknowledge ; Delay--wait for data transfer ih_1: ; Send master acknowledge ; restore saved registers pop pop sti iret ds ax _isr_handler _TEXT endp ends end Interrupt Handling The INTEN bit of Interrupt Register 2 must be set to enab
Appendix D Register-Level Programming To interrupt the host computer using one of the 82C53 counter outputs, program the counter(s) as described in the section, Interrupt Programming Example for the 82C53, of this chapter. External signals can be used to interrupt the PC-DIO-96/PnP when port A or port B is in mode 0 and the low nibble of port C is configured for input. If port A is in mode 0, use PC3 to generate an interrupt; if port B is in mode 0, use PC0 to generate an interrupt.
Appendix Using Your PC-DIO-96 (Non-PnP) Board E This appendix describes the differences between the PC-DIO-96PnP and PC-DIO-96 boards, the PC-DIO-96 board configuration, and the installation of the PC-DIO-96 into your computer. Read this appendix only if you do not have the Plug and Play version of the board. Differences between the PC-DIO-96PnP and the PC-DIO-96 The PC-DIO-96PnP is a Plug and Play upgrade from a legacy board, the PC-DIO-96.
Appendix E Using Your PC-DIO-96 (Non-PnP) Board Configuration and Installation of the PC-DIO-96 Port A 8 82C55A PPI Port B 8 Port C 8 Port A 8 21 Data Transceiver 82C55A PPI Port B 8 Port C 8 Port A 8 PC I/O Channel Control 82C55A PPI Port B 8 Port C 8 Port A 8 6 Interrupt Control Circuitry 82C55A PPI I/O Connector PC I/O Channel 8 Port B 8 Port C 8 82C53 Timer +5 VDC 1 A Fuse Figure E-1.
Appendix E 3 2 1 2 W2 U16 Using Your PC-DIO-96 (Non-PnP) Board 4 5 1 3 4 6 Serial Number W1 5 6 J1 F1 Figure E-2.
Appendix E Using Your PC-DIO-96 (Non-PnP) Board The PC-DIO-96 is configured at the factory to a base I/O address of hex 180 and to interrupt level 5. These settings (shown in Table E-2) are suitable for most systems. However, if your system has other hardware at this base I/O address or interrupt level, you need to change these settings on the PC-DIO-96 (as instructed on the following pages) or on the other hardware.
Appendix E Using Your PC-DIO-96 (Non-PnP) Board The base I/O address for the PC-DIO-96 is determined by the switches at position U16 (see Figure E-2). The switches are set at the factory for the I/O address hex 180. With this default setting, the PC-DIO-96 uses the I/O address space hex 180 through 19F. Note: Verify that this space is not already used by other equipment installed in your computer.
Appendix E Using Your PC-DIO-96 (Non-PnP) Board U16 1 OFF A9 2 A8 3 A7 4 A6 5 A5 Switches Set to Default Setting (Base I/O Address Hex 180) U16 1 OFF A9 A8 2 A7 3 A6 4 A5 5 Switches Set to Base I/O Address Hex 2A0 Figure E-3. Example Base I/O Address Switch Settings Table E-3 shows all possible switch settings and their corresponding address ranges.
Appendix E Table E-3.
Appendix E Using Your PC-DIO-96 (Non-PnP) Board Table E-3.
Appendix E Using Your PC-DIO-96 (Non-PnP) Board W2 IRQ9 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 Figure E-4. Interrupt Jumper Setting for IRQ5 (Default Setting) The PC-DIO-96 can share interrupt lines with other devices because it uses a tri-state driver to drive its selected interrupt line. For information on how to disable this driver, see Appendix D, Register-Level Programming. Installation You can install the PC-DIO-96 in any unused 8-bit, 16-bit, or 32-bit expansion slot in your computer.
Appendix E Using Your PC-DIO-96 (Non-PnP) Board Note: 6. Visually verify the installation. 7. Replace the cover to the computer. If you have an ISA-class computer and you are using a configurable software package, such as NI-DAQ, you may need to reconfigure your software to reflect any changes in jumper or switch settings. If you have an EISA-class computer, you need to update the computer's resource allocation (or configuration) table by reconfiguring your computer.
Appendix Customer Communication F For your convenience, this appendix contains forms to help you gather the information necessary to help us solve your technical problems and a form you can use to comment on the product documentation. When you contact us, we need the information on the Technical Support Form and the configuration form, if your manual contains one, about your system configuration to answer your questions as quickly as possible.
FaxBack Support FaxBack is a 24-hour information retrieval system containing a library of documents on a wide range of technical information. You can access FaxBack from a touch-tone telephone at (512) 418-1111. E-Mail Support (currently U.S. only) You can submit technical support questions to the appropriate applications engineering team through e-mail at the Internet addresses listed below. Remember to include your name, address, and phone number so we can contact you with solutions and suggestions.
Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware, and use the completed copy of this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
PC-DIO-96/PnP Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item. Also fill out the hardware and software configuration forms for all modules in the chassis, all relevant DAQ boards, and all other chassis in the application. By completing these forms accurately, our applications engineers will be able to answer your questions efficiently.
Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: PC-DIO-96/PnP User Manual Edition Date: September 1996 Part Number: 320289C-01 Please comment on the completeness, clarity, and organization of the manual.
Glossary Prefix Meaning Value n- nano- 10-9 µ- micro- 10-6 m- milli- 10-3 k- kilo- 103 M- mega- 106 ° degrees Ω ohms % percent +5 V +5 volt signal A amperes ACK* acknowledge input signal AIRQ0 PPI A interrupt request bit for Port A AIRQ1 PPI A interrupt request bit for Port B APA bidirectional data lines for Port A of PPI A APB bidirectional data lines for Port B of PPI A APC bidirectional data lines for Port B of PPI A BCD binary-coded decimal BIRQ0 PPI B interru
Glossary BPA bidirectional data lines for Port A of PPI B BPB bidirectional data lines for Port B of PPI B BPC bidirectional data lines for Port C of PPI B C Celsius CIRQ0 PPI C interrupt request bit for Port A CIRQ1 PPI C interrupt request bit for Port B CMOS complementary metal-oxide semiconductor CPA bidirectional data lines for Port A of PPI C CPB bidirectional data lines for Port B of PPI C CPC bidirectional data lines for Port C of PPI C CTR1 counter 1 enable bit CTRIRQ counter
Glossary IBFB input buffer bit for Port B in.
Glossary RTSI Real-Time System Integration s seconds SCXI Signal Conditioning eXtensions for Instrumentation STB strobe input signal TTL transistor-to-transistor logic V volts VDC volts direct current VEXT external volt Vin volts in VOH volts, output high VOL volts, output low WR* write signal PC-DIO-96/PnP User Manual G-4 © National Instruments Corporation
Index Numbers Port C status-word bit definitions for input, D-15 to D-16 programming example, D-16 to D-17 mode 1 strobed output, D-17 to D-20 control word written to CNFG Register (figure), D-17 to D-18 Port C pin assignments (figure), D-19 Port C status-word bit definitions for output, D-18 programming example, D-19 to D-20 mode 2 operation bidirectional bus, D-21 to D-24 control word written to CNFG Register, D-21 Port C pin assignments (figure), D-23 Port C status-word bit definitions, D-22 programmin
Index A INTRA, D-15, D-18, D-22 INTRB, D-16, D-18 I/O, D-15, D-18, D-22 OBFA*, D-18, D-22 OBFB*, D-18 block diagram PC-DIO-96, E-2 PC-DIO-96/PnP, 4-1 board configuration. See configuration. BPA<7..0> signal (table), 3-3 BPB<7..0> signal (table), 3-3 BPC<7..0> signal (table), 3-3 bulletin board support, F-1 ACK* signal description (table), 3-13 mode 1 output timing (figure), 3-15 mode 2 bidirectional timing (figure), 3-16 AIRQ0 bit, D-9 AIRQ1 bit, D-9 APA<7..0> signal (table), 3-3 APB<7..
Index digital I/O specifications, A-1 to A-2 digital logic level specifications, A-1 digital power-up state selection. See digital I/O power-up state selection. DIRQ0 bit, D-8 DIRQ1 bit, D-8 documentation conventions used in manual, x-xi National Instruments documentation, xii organization of manual, ix-x related documentation, xiii DPA<7..0> signal (table), 3-3 DPB<7..0> signal (table), 3-3 DPC<7..
Index G INTEN bit description, D-10 interrupt handling, D-35 Interrupt Control Register Group, D-7 to D-10 Interrupt Control Register 1, D-8 to D-9 Interrupt Control Register 2, D-10 overview, D-7 register map, D-3 interrupt handling, D-35 to D-36 interrupt level selection PC-DIO-96, E-8 to E-9 factory settings (table), E-4 IRQ5 default setting (figure), E-9 PC-DIO-96/PnP, 2-3 interrupt programming examples 82C53 Programmable Interval Timer, D-27 to D-35 82C55A Programmable Peripheral Interface, D-23 to D
Index J mode 1 strobed output, 82C55A Programmable Peripheral Interface, D-17 to D-20 control word written to CNFG Register (figure), D-17 to D-18 Port C pin assignments (figure), D-19 Port C status-word bit definitions for output, D-18 programming example, D-19 to D-20 purpose and use, D-11 mode 2 bidirectional timing (figure), 3-16 mode 2 operation, 82C55A Programmable Peripheral Interface bidirectional bus, D-21 to D-24 control word written to CNFG Register, D-21 Port C pin assignments (figure), D-23 P
Index P power connections, 3-9 power requirements, A-2 programming. See register-level programming. parts locator diagram PC-DIO-96, E-3 PC-DIO-96/PNP, 2-1 PC-DIO-96 compared with PC-DIO-96/PnP, E-1 configuration. See configuration.
Index mode 1 strobed output, D-17 to D-20 control word written to CNFG Register (figure), D-17 to D-18 Port C pin assignments (figure), D-19 Port C status-word bit definitions for output, D-18 programming example, D-19 to D-20 mode 2 operation bidirectional bus, D-21 to D-24 control word written to CNFG Register, D-21 Port C pin assignments (figure), D-23 Port C status-word bit definitions, D-22 programming example, D-23 to D-24 purpose and use, D-12 single-bit reset feature, D-12 compared with other softw
Index W SSR-OAC-5 or SSR-OAC-5A output modules, driving with PC-DIO-96/PnP (note), 1-2 starting to use PC-DIO-96/PnP, 1-2 STB* signal description (table), 3-13 mode 1 input timing (figure), 3-14 mode 2 bidirectional timing (figure), 3-16 switches. See jumper and switch settings, PC-DIO-96.
