Specifications

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1-1 4

Bhapter 1 BIOS SettpBhapter 1 BIOS Settp

Bhapter 1 BIOS Settp

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◎ Figure 4. Advanced Chipset Features

Advanced Chipset Features

This section allows you to configure the system based on

the specific features of the installed chipset. This chipset

manages bus speeds and access to system memory resources,

such as DRAM and external cache. It also coordinates

communications of the PCI bus. It must be stated that these

items should never need to be altered. The default settings

have been chosen because they provide the best operating

conditions for your system. The only time you might

consider making any changes would be if you discovered that

data was lost while using your system.

DRAM Timing Selectable By SPD Item Help

DRAM Latency Time 2.5

Active to Precharge Delay 7 Menu Level

DRAM RAS# to CAS# Delay 3

DRAM RAS# Precharge 3

DRAM Data Integrity Mode Non-ECC

Memory Frequency For Auto

Buffer Strength Control Press Enter

DRAM Read Thermal Mgnt Disabled

System BIOS Cacheable Enabled

Video BIOS Cacheable Disabled

Video RAM Cacheable Disabled

Memory Hole At 15M-16M Disabled

Delayed Transaction Enabled

Delay Prior to Thermal 16 Min

AGP Aperture Size (MB) 64

←→↑↓: Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit

F1:General Help F5:Previous Values F6:Fail-Safe Defaults

F7:Optimized Defaults

2.4 Advanced Chipset Features2.4 Advanced Chipset Features

2.4 Advanced Chipset Features

DRAM Timing Selectable

The DRAM timing is controlled by the DRAM Timing

Registers. The Timings programmed into this register are

dependent on the system design.

The Choices: By SPD(default), Manual.