Product Info
ABLUE TECHNOLOGY
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All pins can be used by the PPI task/event system; the maximum number of pins that can be
interfaced through the PPI at the same time is limited by the number of GPIOTE channels
All pins can be individually configured to carry serial interface or quadrature demodulator signals
Hardware RESET:
There is on-chip power-on reset circuitry, But can still be used in external reset mode, in this case, GPIO
pin P0.18 as an external hardware reset pin. In order to utilize P0.18 as a hardware reset, the UICR registers
PSELRESET[0] and PSELRESET[1] must be set alike, to the value of 0x7FFFFF12. When P0.18 is
programmed as RESET, the internal pull-up is automatically enabled.
HW debug and flash programming of Module :
The Module support the two pin Serial Wire Debug (SWD) interface and offers flexible and powerful
mechanism for non-intrusive debugging of program code. Breakpoints, single stepping, and instruction trace
capture of code execution flow are part of this support.
Pin
Flash Program interface
SWDIO
Debug and flash programming I/O
SWDCLK
Debug and flash programming I/O
This is the hardware debug and flash programming of module, J-Link Lite support, please refer
www.segger.com.
Power and Configuration:
The module has two internal regulator stages. REG1 regulator stage has the regulator type options of
Low-dropout regulator (LDO) and Buck regulator (DC/DC). REG0 regulator stage has only the option of
Low-dropout regulator (LDO). The first regulator, REG0, is fed by the VDDH pin and can accept a source
voltage of 2.5 V to 5.5 V. The output of REG0 is connected to the VDD pin and the input of the second
regulator stage REG1. REG1 supplies power to the module core and can accept an input source voltage of 1.7V
to 3.6V. Depending on how the VDD and VDDH pins are connected, the module will operate in one of two
modes: Normal/Low Voltage (LV) or High Voltage (HV). The voltage present on the VDD pin is always the
GPIO high logic level voltage, regardless of power mode.
To enter LV Mode, the same source voltage is applied to both the VDD and VDDH pins causing REG0 to
automatically shut down leaving only the REG1 stage active. To enter HV, the source voltage is only applied to
VDDH causing the VDD pin to become an output source supplied by REG0.
Mode
Pin of Module
Name
Power Connection
Normal/Low Voltage (LV)
Pin 23
VDD
1.7V to 3.6V source in
Pin 13
VDDH
Same source as VDD
High Voltage (HV)
Pin 23
VDD
1.8V to 3.3V supply out
Pin 13
VDDH
2.5V to 5.5V source in
Important: In both LV and HV modes, the GPIO logic level voltage is determined by the VDD pin. In
HV mode, all external devices that are connected to the Module’s GPIO must either be powered by the module
(from VDD) or use level translation.