Specifications

SWITCHING CHARACTERISTICS (T
A
= 25°C; VA, VD = +5V, outputs loaded with 30 pF; Input
Levels: Logic 0 = 0V, Logic 1 = VD)
Parameter Symbol Min Typ Max Units
Input clock (CLKIN) frequency SM3 Multiplier Mode CLKIN 64 768 800 KHz
SM3 Master and Slave Modes, SM4, SM5 CLKIN 1.024 12.288 12.8 MHz
CLKIN low time t
ckl
15 - - ns
CLKIN high time t
ckh
15 - - ns
Sample Rate (Note 1) Fs 4 - 50 kHz
DI pins setup time to SCLK edge (Note 1) t
s2
10 - - ns
DI pins hold time from SCLK edge (Note 1) t
h2
8--ns
DO pins delay from SCLK edge t
pd2
- - 30 ns
SCLK and SSYNC output
All master Modes (Note 1) t
pd3
- - 50 ns
delay from CLKIN rising
SCLK period All master Modes (Notes 1,7) t
sckw - 1/(Fs*bpf) - s
Slave Mode
75 - - ns
SCLK high time Slave Mode t
sckh
30 - - ns
SCLK low time Slave Mode t
sckl
30 - - ns
SDIN, SSYNC setup time to SCLK edge Slave Mode t
s1
15 - - ns
SDIN, SSYNC hold time from SCLK edge Slave Mode t
h1
10 - - ns
SDOUT delay from SCLK edge t
pd1
- - 28 ns
Output to Hi-Z state bit 64 (Note 1) t
hz
- - 12 ns
Output to non-Hi-Z bit 1 (Note 1) t
nz
15 - - ns
RESET pulse width low 500 - - ns
CCS low to CCLK rising SM4 (Note 1) t
cslcc
25 - - ns
CDIN setup to CCLK falling SM4 (Note 1) t
discc
15 - - ns
CCLK low to CDIN invalid (hold time) SM4 (Note 1) t
ccdih
10 - - ns
CCLK high time SM4 (Note 1) t
cclhh
25 - - ns
CCLK low time SM4 (Note 1) t
cclhl
25 - - ns
CCLK Period SM4 (Note 1) t
cclkw
75 - - ns
CCLK rising to CDOUT data valid SM4 (Note 1) t
ccdov
- - 30 ns
CCLK rising to CDOUT Hi-Z SM4 (Note 1) t
ccdot
- - 30 ns
CCLK falling to CCS high SM4 (Note 1) t
cccsh
0--ns
RESET low time prior to PDN rising trph 100 - - ns
RESET low hold time after PDN rising trhold 50 - - ms
Notes: 7. When the CS4218 is in master modes (SSYNC and SCLK outputs), the SCLK duty cycle is 50%.
The equation is based on the selected sample frequency (Fs) and the number of bits per frame (bpf).
CS4218
DS135F1 5