Specifications

SCLK must be generated externally. When the
codec is the serial port master, the serial port sig-
nal transitions are controlled with respect to the
internal analog sampling clock to minimize the
amount of digital noise coupled into the analog
section. Since SSYNC and SCLK are externally
derived when the codec slaves to the serial port,
optimum noise management cannot be obtained;
therefore, master modes should be used when-
ever possible. Multiplier sub-modes are identical
to the SM3 modes except the master clock,
CLKIN, is internally multiplied by 16. A
0.47 µF capacitor must be tied to the FILT pin
when using the Multiplier sub-modes.
Master Clock Frequency
In SM3-M and SM3-S sub-modes, the master
clock, CLKIN, must be 256 × Fs
max
. For exam-
ple, given a 48 kHz maximum sample frequency,
the master clock frequency must be
12.288 MHz. In SM3-MM and SM3-MS sub-
modes, CLKIN must be 16xFs
max
. For
example, given a 48 kHz maximum sample fre-
quency, the master clock frequency must be
768 kHz. SCLK and SSYNC must be synchro-
nous to the master clock.
Sub-frame
Word B
Word A
DAC - Left Word
00 0 0
00
DAC - Right Word
DO1
DO2
00
MSB
LSB MSB LSB
MUTE
ISL ISR
LG3 LG2 LG1 LG0 RG3 RG2 RG1 RG0
LA4 LA3 LA2 LA1 LA0
RA4 RA3 RA2 RA1 RA0
0
64 01 16 17 21 24 25 28 29 32 22 23 33 52 48 53 56 57 60 61 55 51 34 35 36 37 38 39 40 41 42 43 44 45 46 47 14 15 12 13 10 11 09 07 08 05 06 03 04 02 19 20 18 26 27 30 31 50 49 54 58 59 62 63
Sub-frame
Figure 11. Serial Data Input Format - SM3, SM5.
64
Sub-frame
Word B
Word A
ADC - Left Word
0
ADC - Right Word
DI1 DI2
X
MSB
LSB
ADV
LCL
RCL
MSB
LSB
00010000
01 16 17 21 24 25 28 29 32 22 23 33 52 48 53 56 57 60 61 55
0000
0000
51 34 35 36 37 38 39 40 41 42 43 44 45 46 47 14 15 12 13 10 11 09 07 08 05 06 03 04 02 19 20 18 26 27 30 31 50 49 54 58 59 62 63
ER3 ER2 ER1 ER0
VER3 VER2 VER1 VER0
DI3
Sub-frame
Figure 12. Serial Data Output Format - SM3, SM5.
CS4218
16 DS135F1