CS4218 16-Bit Stereo Audio Codec Complete CMOS Stereo Audio Input and Output System featuring: General Description The CS4218 Stereo Audio Codec is a monolithic CMOS device for computer multimedia, automotive, and portable audio applications. It performs A/D and D/A conversion, filtering, and level setting, creating 4 audio inputs and 2 audio outputs for a digital computer system.
CS4218 Contents Description Cover . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . Analog Input Characteristics . . . . . . . . Analog Output Characteristics . . . . . . . Switching Characteristics . . . . . . . . . Digital Characteristics . . . . . . . . . . A/D Decimation Filter Characteristics . . . . . . D/A Interpolation Characteristics . . . . . . . Absolute Maximum Ratings . . . . . . . . Filter Response Plots . . . . . . . . . .
CS4218 RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, all voltages with respect to 0V.) Parameter Power Supplies: Digital Digital (Low Voltage) Analog Operating Ambient Temperature Symbol Min Typ Max Units VD VD VA 4.75 3.0 4.75 5.0 3.3 5.0 5.25 3.6 5.25 V V V TA 0 25 70 °C ANALOG CHARACTERISTICS( TA = 25°C; VA, VD = +5V; Input Levels: Logic 0 = 0V, Logic 1 = VD; 1kHz Input Sine Wave; CLKIN = 12.
CS4218 ANALOG CHARACTERISTICS (Continued) Parameter * Symbol Min Typ Max Units 16 - - Bits - - ±0.9 LSB Analog Output Characteristics - Minimum Attenuation; Unless Otherwise Specified. DAC Resolution DAC Differential Nonlinearity (Note 1) Total Dynamic Range TDR - 93 - dB Instantaneous Dynamic Range IDR 80 83 - dB THD - - 0.02 % - 80 - dB - - ±0.
CS4218 SWITCHING CHARACTERISTICS (TA = 25°C; VA, VD = +5V, outputs loaded with 30 pF; Input Levels: Logic 0 = 0V, Logic 1 = VD) Parameter Symbol Min Typ Max Units Input clock (CLKIN) frequency SM3 Multiplier Mode SM3 Master and Slave Modes, SM4, SM5 CLKIN CLKIN 64 1.024 768 12.288 800 12.
CS4218 t sckw SCLK [SM3,SM4\ t sckh t sckl t s1 t h1 SSYNC [SM3,SM4\ t h1 t s1 [SM3] (SM4) SDIN Bit 1 Bit 2 SDOUT Bit 33 (Bit 1) Bit 32 (Bit 32) Bit 33 (Bit 1) Bit 63 (Bit 31) Bit 64 (Bit 32) t pd1 t pd1 [SM3] Bit 32 (Bit 32) Bit 2 Bit 1 (SM4) Bit 63 (Bit 31) t hz Bit 64 (Bit 32) t nz Serial Audio Port Timing MF4:CCS LCL ADV MF1:CDOUT t cslcc t cclkl t cclkh t ccdov MF3:CCLK t ccdih t discc t cclkw 0 MSK DO1 LAtt4 LAtt3 LAtt2 LAtt1 LAtt0 RAtt4 1 2 3 4 5 6 7 8
CS4218 SCLK t s2 t h2 t ckl DIx t ckh CLKIN t pd2 t pd3 SCLK SSYNC (Master Mode) DOx DI/DO Timing SCLK & SSYNC Output Timing (Master Mode) PDN t rhold t rph RESET Power Down Mode Timing DIGITAL CHARACTERISTICS (TA = 25°C; VA = 5V, VD = 5V or 3.3V) Parameter Symbol Min Typ Max Units High-level Input Voltage VIH 2.0 - VD+0.3 V Low-level Input Voltage VIL -0.3 - 0.8 V High-level Output Voltage at I0 = -2.0 mA VOH VD-0.3 - - V Low-level Output Voltage at I0 = +2.
CS4218 A/D Decimation Filter Characteristics Parameter Symbol Min Typ Max Units 0 - 0.40Fs Hz -0.5 - +0.2 dB - - ±0.1 dB Transition Band 0.40Fs - 0.60Fs Hz Stop Band 0.60Fs - - Hz 74 - - dB Passband Frequency Response Passband Ripple (0-0.4Fs) Stop Band Rejection Group Delay - 8/Fs s Group Delay Variation vs. Frequency - 0.0 µs D/A Interpolation Filter Characteristics Parameter Symbol Min Typ Max Units 0 - 0.40Fs Hz -0.5 - +0.2 dB - - ±0.
CS4218 10 0.2 0 0.1 -10 -0.0 -0.1 Magnitude (dB) Magnitude (dB) -20 -30 -40 -50 -60 -0.2 -0.3 -0.4 -0.5 -70 -80 -0.6 -90 -0.7 -100 -0.8 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.00 0.05 Input Frequency (×Fs) Figure 2. CS4218 ADC Passband Ripple 0 10 -10 0 -20 -10 -30 -20 -30 Magnitude (dB) Magnitude (dB) 0.50 Input Frequency (×Fs) Figure 1. CS4218 ADC Frequency Response -40 -50 -60 -70 -40 -50 -60 -80 -70 -80 -90 -90 -100 -100 0.0 0.1 0.2 0.3 0.4 0.5 0.
CS4218 2.5 2.0 Phase (degrees) 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Input Frequency (×Fs) Figure 7.
CS4218 Ferrite Bead +5V Supply 2.0 1 µF + 0.1 µF + 24 4 VD Line In 2 Right 26 +5V Analog 0.1 µF 1 µF If a separate +5V Analog supply is used, remove the 2.0 ohm resistor VA 15 + ROUT RIN2 > 1.0 µF 40 k Right Audio Output 0.0022µF NPO See Analog Inputs section for suggested input ciruits. 16 + LOUT > 1.0 µF 40 k 28 Line In 2 Left Left Audio Output 0.0022µF NPO LIN2 21 REFBYP 0.
CS4218 OVERVIEW The CS4218 contains two analog-to-digital converters, two digital-to-analog converters, adjustable input gain, and adjustable output level control. Since the converters contain all the required filters in digital or sampled analog form, the filters’ frequency responses track the sample rate of the CS4218. Only a single-pole RC filter is required for the analog inputs and outputs. Communication with the CS4218 is via a serial port, with separate pins for data input and output.
CS4218 When using the CS4218 as a drop-in replacement for the CS4216, the external 600 ohm series resistors on LOUT and ROUT are not required, since they are part of the CS4218 internal circuitry. In applications where both CS4218 and CS4216 are to be used, a board stuff option should be included in the bill of materials which will allow either a 600-ohm or a 0-ohm resistor to be used externally on both LOUT and ROUT.
CS4218 master and slave modes automatically initiates a calibration. An RC filter with a time constant greater than 50 ms may be used on the RESET pin. The CS4218 RESET pin has hysterisis to ensure proper resets when using an RC filter. Hard power down mode may be initiated by bringing the PDN pin low. All analog outputs will be driven to the REFBUF voltage which will then decay to zero. All digital outputs will be driven low and then will go to a high impedance state.
CS4218 first, 2’s complement format. Sub-frame bit assignments are shown in Figure 13. Control data bits all reset to zero. the master CLKIN is multiplied internally by 16, so a 16xFs input clock must be provided. SERIAL MODE 3, (SM3) CS4218 SERIAL INTERFACE MODES The CS4218 has three serial port modes, selected by the SMODE1, SMODE2 and SMODE3 pins. In all modes, CLKIN, SCLK and SSYNC must be derived from the same clock source.
CS4218 SCLK must be generated externally. When the codec is the serial port master, the serial port signal transitions are controlled with respect to the internal analog sampling clock to minimize the amount of digital noise coupled into the analog section. Since SSYNC and SCLK are externally derived when the codec slaves to the serial port, optimum noise management cannot be obtained; therefore, master modes should be used whenever possible.
CS4218 SM3 and SM5 Subframe Bit Definitions for SDIN Bit(s) Symbol Description 1-16 DAC-LEFT Audio Data, DAC Left 2’s Complement data, MSB first (Bit 1 = MSB) 17-21 unused Unused, write with 0’s 22 MUTE Mute DAC Outputs 0 = Outputs ON 1 = Outputs MUTED 23 ISL 24 ISR Input Mux, Left Select 0 = LIN1 1 = LIN2 Input Mux, Right Select 0 = RIN1 1 = RIN2 25-28 LG3 - LG0 Left Input Gain 1.5dB Increments. 0000 = No gain (0dB) 1111 = 22.5 dB gain 29-32 RG3 - RG0 Right Input Gain 1.5dB Increments.
CS4218 Master Sub-Mode (SM3-M) Master su b-mod e is selected by setting MF4:MA = 1, which configures SSYNC and SCLK as outputs from the CS4218. During power down, SSYNC and SCLK are driven high impedance, and during reset they both are driven low. In Master sub-mode the number of bits per frame determines how many codecs can occupy the serial bus and is illustrated in Figure 14. Bits Per Frame (Master Sub-Modes) MF8:SFS2 selects the number of bits per frame.
CS4218 FRAME n 128 SCLK Periods Sub-frame 1 DATA Word A Word B FRAME (n+2) Sub-frame 2 Word A Word A Word B Sub-frame 1 Sub-frame 2 Sub-frame 1 Word B FRAME (n+3) Word A Word B Word A Word B MF8: MF7: SubSFS2 SFS1 frame 1 1 0 1 1 2 SSYNC FRAME n 64 SCLK Periods Sub-frame 1 Word A DATA Word B FRAME (n+2) FRAME (n+1) Sub-frame 1 Word A FRAME (n+3) Sub-frame 1 Word B Word A Word B Sub-frame 1 Word A Word B FRAME (n+4) Sub-frame 1 Word A Word B MF8: MF7: SubSFS2 SFS1 frame 0
CS4218 Slave Sub-Mode (SM3-S) lecting the particular sub-frame. MF8:SFS2 must be set to zero. See Figure 17. In SM3, Slave sub-mode is selected by setting MF4:MA = 0 which configures SSYNC and SCLK as inputs to the CS4218. These two signals must be externally derived from CLKIN. In SM3-S and SM3-MS sub-modes, the phase relationship between SCLK/SSYNC and CLKIN cannot be controlled since SCLK and SSYNC are externally derived.
CS4218 ignored and the sample frequency is linearly scaled with SCLK. (The CLKIN pin must be tied low.) This mode also fixes SCLK at 256 bits per frame with MF7:SFS1 and MF8:SFS2 selecting the particular sub-frame. This master clocking option is not available in the multiplier (SM3-MS) sub-mode. Multiplier Sub-Modes (SM3-MM and SM3-MS) Sub-frame 1 DATA Word A Word B FRAME (n+1) Sub-frame 1 Word A Word B Set SMODE1 = SMODE2 = SMODE3 = 0. This selects SM3 Multiplier mode.
CS4218 SERIAL MODE 4, (SM4) Master Sub-Mode (SM4) Serial Mo de 4 is en ab led by setting SMODE3 = 1. Both Master and Slave submodes are available and are selected by setting the SMODE2 and SMODE1 pins as shown in Table 6. In Master sub-mode, the phase relationship between SCLK/SSYNC and CLKIN is controlled to minimize digital noise coupling into the analog section. Therefore, Master submo de may yield slightly better noise performance than Slave sub-mode.
CS4218 In Master sub-mode, multifunction pins MF6:F1, MF7:F2, and MF8:F3 select the sample frequency as shown in Table 7. This table indicates how to obtain standard audio sample frequencies given on e of two CLKIN freq uencies: 12.288 MHz or 11.2896 MHz. Other CLKIN frequencies may be used with the corresponding sample frequencies being CLKIN/N. A change in sample rate automatically initiates a calibration cycle.
CS4218 Serial Control Port (SM4) format is illustrated in Figure 20. The control port uses one of the multifunction pins as a chip select line, MF4:CCS, that must be low for entering control data. Although only 23 bits contain useful data on MF2:CDIN, a minimum of 31 bits must be written. If more than 31 bits are written without toggling MF4:CCS, only the first 31 are recognized. MF1:CDOUT contains status information that is output on the rising edge of MF3:CCLK.
CS4218 SERIAL MODE 5 (SM5) Sample Frequency Selection The Serial Mode 5 is compatible with the Phillips I2S serial protocol. SM5 is enabled by setting SMODE3 = 0, SMODE2 = 0, and SMODE1 = 1. This is a master mode fixed at 64 BPF. The multifunction pins MF1:F1, MF2:F2, and MF3:F3 are used to select the sample frequency divider. Table 3 lists the decoding for the sample frequency select pins where the sample frequency selected is CLKIN/N.
CS4218 Power Supply and Grounding The CS4218, along with associated analog circuitry, should be positioned in an isolated section of the circuit board, and have its own, separate, ground plane. On the CS4218, the analog and digital grounds are internally connected; therefore, the AGND and DGND pins must be externally connected with no impedance between them. The best solution is to place the entire chip on a solid ground plane as shown in Figure 23. Preferably, it should also have its own power plane.
CS4218 >1/8" Digital Ground Plane Analog Ground Plane Ground Connection Note that the CS4218 is oriented with its digital pins towards the digital end of the board. CS4218 Power Connection use Ferrite Bead CPU & Digital Logic Codec digital signals Codec analog signals & Components 1.0 uF 0.1 uF Figure 23. CS4218 Board Layout Guideline + Analog Supply 0.1 uF + 10 uF + 0.1 uF Digital Supply 1.0 uF 1 Figure 24.
0.1 uF CS4218 + 1.0 uF 1 + 1.0 uF 0.1 uF 0.1 uF Digital Supply Analog Supply + 10 uF Figure 25.
CS4218 PIN DESCRIPTIONS SSYNC RESET CLKIN VD DGND FILT NC NC NC NC NC NC PDN NC ROUT LOUT NC NC NC REFBUF REFBYP REFGND 44 42 1 2 3 4 5 6 7 8 9 10 11 40 38 36 34 33 32 31 30 29 28 27 26 25 24 23 CS4218 44-PIN TQFP (Q) Top View 12 14 16 18 20 22 SCLK SDOUT SDIN SMODE3 MF1:F1/CDOUT MF2:F2/CDIN MF5:DO2/INT DO1 MF4:MA/CCS MF3:DI3/F3/CCLK MF6:DI2/F1 DI1 SMODE2 MF7:SFS1/F2 MF8:SFS2/F3 SMODE1 LIN2 LIN1 RIN2 RIN1 VA AGND SM SM5 MF1 F1 MF2 F2 MF3 F3 MF4 Tie to VD MF5 DO2 MF6 DI2 3-SL F1 F2
CS4218 SSYNC RESET CLKIN VD DGND FILT NC NC NC NC NC NC PDN NC ROUT LOUT NC NC NC REFBUF REFBYP REFGND 7 8 9 10 11 12 13 14 15 16 17 6 4 2 1 44 42 40 26 28 CS4218 CS4216 44-PIN PLCC (L) Top View 18 20 22 24 39 38 37 36 35 34 33 32 31 30 29 SCLK SDOUT SDIN SMODE3 MF1:F1/CDOUT MF2:F2/CDIN MF5:DO2/INT DO1 MF4:MA/CCS MF3:DI3/F3/CCLK MF6:DI2/F1 DI1 SMODE2 MF7:SFS1/F2 MF8:SFS2/F3 SMODE1 LIN2 LIN1 RIN2 RIN1 VA AGND SM SM5 MF1 F1 MF2 F2 MF3 F3 MF4 tie to VD MF5 DO2 MF6 DI2 MF7 tie to DGND MF
CS4218 AGND - Analog Ground, PIN 23(L), 17(Q). Analog ground. Must be connected to DGND with zero impedance. Analog Inputs RIN1 - Right Input #1, PIN 25(L), 19(Q). Right analog input #1. Full scale input, with no gain, is 1Vrms, centered at REFBUF. RIN2 - Right Input #2, PIN 26(L), 20(Q). Right analog input #2. Full scale input, with no gain, is 1Vrms, centered at REFBUF. LIN1 - Left Input #1, PIN 27(L), 21(Q). Left analog input #1. Full scale input, with no gain, is 1Vrms, centered at REFBUF.
CS4218 SSYNC - Serial Port Sync Signal, PIN 1(L), 39(Q). Indicates the start of a digital audio frame. SSYNC must be synchronous to the master clock. SMODE1 - Serial Mode Select, PIN 29(L), 23(Q). One of three pins that select the serial mode and function of the multifunction pins. SMODE2 - Serial Mode Select, PIN 32(L), 26(Q). One of three pins that select the serial mode and function of the multifunction pins. SMODE3 - Serial Mode Select, PIN 41(L), 35(Q).
CS4218 MF4:CCS - Control Data Chip Select in SM4, PIN 36(L), 30(Q). In SM4 this pin is the control port chip select signal. When low, the control port data is clocked in CDIN and status data is output on CDOUT. When CCS goes high, control data is latched internally. This data remains active until new data is clocked in. The control port may also be asynchronous to the audio data port. MF5:DO2 - Parallel Digital Bit Output #2 in SM3 and SM5, PIN 38(L), 32(Q).
CS4218 Miscellaneous RESET - Reset Input, PIN 2.(L), 40(Q). Resets the CS4218 to a known state, and must be initiated after power-up or power-down mode. Releasing RESET causes the CS4218 to initiate a calibration sequence. The CS4218 automatically initiates a calibration sequence after a sample rate change in master and slave modes. CLKIN - Master Clock, PIN 3(L), 41(Q). CLKIN is the master clock that operates the internal logic.
CS4218 PACKAGE DIMENSIONS 44 PIN PLCC NO. OF A TERMINALS MIN MAX 17.40 17.65 (0.685) (0.695) 44 B C MIN MAX 16.51 16.66 (0.650) (0.656) MIN MAX 14.98 16.00 (0.590) (0.630) B 4.62 (0.182) 4.11 (0.162) 1.14 (0.045) 0.63 (0.025) 1.27(0.050) x45deg.NOM 2.41 (0.095) MIN A 1.14 (0.045) x 45deg. NOM B A 0.25 (0.010) R MAX C 1.35 (0.053) 1.19 (0.047) 0.46 ( 0.018 ) 0.33 ( 0.013 ) 3 NOM 3 NOM ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES.
CS4218 PARAMETER DEFINITIONS Resolution The number of bits in the input words to the DACs, and in the output words from the ADCs. Differential Nonlinearity The worst case deviation from the ideal codewidth. Units in LSB. Total Dynamic Range TDR is the ratio of the rms value of a full scale signal to the lowest obtainable noise floor. It is measured by comparing a full scale signal to the lowest noise floor possible in the codec (i.e. attenuation bits for the DACs at full attenuation). Units in dB.
CS4218 Out of Band Energy The ratio of the rms sum of the energy from 0.46×Fs to 2.1×Fs compared to the rms full-scale signal value. Tested with 48 kHz Fs giving a out-of-band energy range of 22 kHz to 100 kHz.
CS4218 Appendix A: CS4218 Compatibility with CS4216 IMPORTANT !! If you are upgrading your design from the CS4216 to the CS4218, please make sure to read this entire appendix. The CS4218 is pin compatible with the CS4216. This appendix provides a summary of differences between the two codecs. Pin Compatibility The CS4218 is 100% pin compatible with the CS4216 when used in Serial Modes 3 and 4. The differences are noted in the following paragraphs and tables.
CS4218 Parameter Passband Passband Ripple Transition Band Stop Band Stop Band Rejection Group Delay Units Hz dB Hz Hz dB sec CS4218 0-0.4Fs ± 0.1 0.4-0.6Fs 0.6Fs 74dB 8/Fs TABLE A1: Decimation Filter Comparison CS4216 0-0.45Fs ± 0.2 0.45-0.55 0.55Fs 80dB 16/Fs Parameter Passband Passband Ripple Transition Band Stop Band Stop Band Rejection Group Delay Units Hz dB Hz Hz dB sec CS4218 0-0.4Fs ± 0.1 0.4-0.6Fs 0.6Fs 74dB 8/Fs TABLE A2: Interpolation Filter comparison CS4216 0-0.45Fs ± 0.1 0.45-0.55 Fs 0.
CS4218 Appendix B: Applications of SM4 Figure B1 illustrates one method of using Serial Mode 4 wherein a DSP controls the audio serial port and a microcontroller controls the control port. Each controller is run independently and the micro updates the control information only when needed, or when an interrupt from the CS4218 occurs. Figure B2 illustrates the minimum interface to the CS4218. In this application, the DSP sends and receives stereo DAC and ADC information.
CS4218 43 SDOUT 42 SDIN 1 SSYNC 44 DSP SCLK VD+ 35 MF3:CCLK 36 MF4:CCS 38 MF5:INT 39 MF2:CDIN HC597 HC597 HC597 DIN DOUT LOAD CS4218 SM4 A B LCLK C D AIN E F HC595 G H OE SCLK 32 BPF 40 MF1:CDOUT 0 ADV DI1 RCL LCL ERR0 ERR1 1 CS^CONTROL 24+ bit DSP Data Bus CS^STATUS 2 CS^FS RESET 34 MF6:F1 31 MF7:F2 30 MF8:F3 HC574 Figure B3.
CS4218 To load control data into the codec, three HC597’s are utilized. These are the latches that store the DSP-sent control data, and shift registers that shift the data into the codec. The codec uses an inverted SSYNC signal to copy the latches to the shift registers every frame. In this diagram the DSP is assumed to have a data bus bandwidth of at least 24 bits. If the DSP has less than 24-bits, the three HC597s must be split into two addresses.
CS4218 Appendix C: Setting CLKIN/SCLK Ratio for Desired Sample Rate In Slave sub-modes, the CS4218 detects the ratio between the CLKIN and SCLK rates and sets the internal sample rate accordingly. The following formula can be used to determine the ratio of CLKIN to SCLK for any desired sample rate for both Serial Modes 3 and 4, Slave sub-modes. CLKIN (256 × Fsmax) = SCLK (BPF × Fs) where: CLKIN = Master clock input In SM3 Multiplier Slave sub-mode, CLKIN is replaced by 16* CLKIN.
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