User`s manual

BIOS Setup 3-13
 Back to Advanced Chipset Features Setup Menu:
CPU & PCI Bus Control:
Click <Enter> key to enter its submenu:
PCI Master 0 WS Write:
Two options are available: Enabled or Disabled. The default setting is Enabled. When Enabled, writes to
the PCI bus are executed with zero wait state (immediately) when PCI bus is ready to receive data. If it is
set to Disabled, the system will wait one state before data is written to the PCI bus.
PCI Master 0 WS Read:
Two options are available: Enabled or Disabled. The default setting is Enabled. When Enabled, reads to
the PCI bus are executed with zero wait state (immediately) when PCI bus is ready to receive data. If it is
set to Disabled, the system will wait one state before data is written to the PCI bus.
CPU to PCI Post Write
Two options are available: Enabled or Disabled. The default is Enabled, When Enable, data transmission
from CPU to PCI bus are buffered and compensate for the different speed between CPU and PCI bus. If it
is set to Disabled, data transmissions are not buffered and CPU must wait until the data transmission is
complete and then start another transmission cycle.
Vlink 8X Support:
Two options are available: Disabled or Enabled. The default setting is Enabled. This item can let you
enable the Vlink bus data transfer between northbridge and southbridge.
PCI Delay Transaction:
Two options are available: Disabled or Enabled. The default setting is Enabled. The chipset has an
embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support
compliance with PCI specification version 2.2.
User’s Manual