Circuit diagram
CRC_error:
When you use the dedicated CRC_ERROR pin configured as an open-drain output, connect
this pin through an external 10-kΩ pull-up resistor to VCCPGM.
When you do not use the dedicated CRC_ERROR pin configured as an open-drain output and
when this pin is not used as an I/O pin, connect this pin as defined in the Quartus II software.
(PCG-01014-1.7)
LVDS or SE
5CEBA2U15
5CEBA2U15
GND
GND
51790_29/30/31_-1
GND
GNDGND
5CEBA2U15
GND
VCCIO_VCCPD
VCCIO_VCCPD
VCCIO_VCCPD
VCCIO_VCCPD
GNDGND GND GND GND GND
VCCIO_VCCPD
GND
+3V3
51790_29/30/31_-1
GND
IO/RZQ_0/DIFFIO_TX_B25N/DIFFOUT_B25N
U13
IO/DIFFIO_RX_B26N/DIFFOUT_B26N/DQ3B
V13
IO/DIFFIO_TX_B25P/DIFFOUT_B25P/DQ3B
U14
IO/DIFFIO_RX_B26P/DIFFOUT_B26P/DQ3B
V12
IO/DIFFIO_RX_B27N/DIFFOUT_B27N/DQSN3B
M14
IO/DIFFIO_TX_B28N/DIFFOUT_B28N/DQ3B
U18
IO/DIFFIO_RX_B27P/DIFFOUT_B27P/DQS3B
L13
IO/DIFFIO_TX_B28P/DIFFOUT_B28P
V17
IO/DIFFIO_TX_B29N/DIFFOUT_B29N/DQ3B
U17
IO/DIFFIO_RX_B30N/DIFFOUT_B30N/DQ3B
V16
IO/DIFFIO_TX_B29P/DIFFOUT_B29P/DQ3B
T17
IO/DIFFIO_RX_B30P/DIFFOUT_B30P/DQ3B
V15
IO/CLK2N/DIFFIO_RX_B31N/DIFFOUT_B31N
U12
IO/DIFFIO_TX_B32N/DIFFOUT_B32N/DQ3B
R18
IO/CLK2P/DIFFIO_RX_B31P/DIFFOUT_B31P
T12
IO/DIFFIO_TX_B32P/DIFFOUT_B32P/DQ3B
P18
IO/DIFFIO_TX_B33N/DIFFOUT_B33N
T16
IO/DIFFIO_RX_B34N/DIFFOUT_B34N/DQ4B
P14
IO/DIFFIO_TX_B33P/DIFFOUT_B33P/DQ4B
R17
IO/DIFFIO_RX_B34P/DIFFOUT_B34P/DQ4B
P15
IO/DIFFIO_RX_B35N/DIFFOUT_B35N/DQSN4B
M13
IO/DIFFIO_TX_B36N/DIFFOUT_B36N/DQ4B
R16
IO/DIFFIO_RX_B35P/DIFFOUT_B35P/DQS4B
N12
IO/DIFFIO_TX_B36P/DIFFOUT_B36P
P16
IO/DIFFIO_TX_B37N/DIFFOUT_B37N/DQ4B
N17
IO/DIFFIO_RX_B38N/DIFFOUT_B38N/DQ4B
R13
IO/DIFFIO_TX_B37P/DIFFOUT_B37P/DQ4B
N16
IO/DIFFIO_RX_B38P/DIFFOUT_B38P/DQ4B
T14
IO/CLK3N/DIFFIO_RX_B39N/DIFFOUT_B39N
N13
IO/DIFFIO_TX_B40N/DIFFOUT_B40N/DQ4B
U15
IO/CLK3P/DIFFIO_RX_B39P/DIFFOUT_B39P
P13
IO/DIFFIO_TX_B40P/DIFFOUT_B40P/DQ4B
T15
VCCIO4A
T18
VCCIO4A
U11
VCCIO4A
U16
VCCIO4A
R15
VREFB4AN0
V11
IC201BANK_4A
IO/RZQ_1/DIFFIO_TX_R1P/DIFFOUT_R1P/DQ1R
L16
IO/INIT_DONE/DIFFIO_RX_R2P/DIFFOUT_R2P
L14
IO/PR_REQUEST/DIFFIO_TX_R1N/DIFFOUT_R1N/DQ1R
L15
IO/CRC_ERROR/DIFFIO_RX_R2N/DIFFOUT_R2N
K13
IO/DIFFIO_RX_R4P/DIFFOUT_R4P/DQ1R
J13
IO/CEO/DIFFIO_TX_R3P/DIFFOUT_R3P/DQ1R
M18
IO/CVP_CONFDONE/DIFFIO_TX_R3N/DIFFOUT_R3N/DQ1R
N18
IO/DIFFIO_RX_R4N/DIFFOUT_R4N/DQ1R
J14
IO/DEV_OE/DIFFIO_TX_R5P/DIFFOUT_R5P
K17
IO/DIFFIO_RX_R6P/DIFFOUT_R6P/DQS1R
G13
IO/DIFFIO_RX_R6N/DIFFOUT_R6N/DQSN1R
H13
IO/DEV_CLRN/DIFFIO_TX_R5N/DIFFOUT_R5N/DQ1R
K16
IO/DIFFIO_TX_R7P/DIFFOUT_R7P/DQ1R
L17
IO/DIFFIO_RX_R8P/DIFFOUT_R8P/DQ1R
J16
IO/DIFFIO_TX_R7N/DIFFOUT_R7N
K18
IO/DIFFIO_RX_R8N/DIFFOUT_R8N/DQ1R
J15
VCCIO5A
K15
VCCIO5A
M16
VREFB5AN0
M17
IC201BANK_5A
C301
100n, 6V3
C302
100n, 6V3
C303
100n, 6V3
C304
100n, 6V3
C306
100n, 6V3
C305
4u7, 6V3
C307
4u7, 6V3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
X301
R301
10k
IO/DIFFIO_TX_B17N/DIFFOUT_B17N
V6
IO/DIFFIO_RX_B18N/DIFFOUT_B18N/DQ2B
U5
IO/DIFFIO_TX_B17P/DIFFOUT_B17P/DQ2B
V7
IO/DIFFIO_RX_B18P/DIFFOUT_B18P/DQ2B
U4
IO/DIFFIO_RX_B19N/DIFFOUT_B19N/DQSN2B
P9
IO/DIFFIO_TX_B20N/DIFFOUT_B20N/DQ2B
T4
IO/DIFFIO_RX_B19P/DIFFOUT_B19P/DQS2B
P10
IO/DIFFIO_TX_B20P/DIFFOUT_B20P
T5
IO/FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTN/DIFFIO_TX_B21N/DIFFOUT_B21N/DQ2B
V8
IO/DIFFIO_RX_B22N/DIFFOUT_B22N/DQ2B
T9
IO/FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTP,FPLL_BL_FB/DIFFIO_TX_B21P/DIFFOUT_B21P/DQ2B
U8
IO/DIFFIO_RX_B22P/DIFFOUT_B22P/DQ2B
R9
IO/CLK1N/DIFFIO_RX_B23N/DIFFOUT_B23N
T11
IO/DIFFIO_TX_B24N/DIFFOUT_B24N/DQ2B
U9
IO/CLK1P/DIFFIO_RX_B23P/DIFFOUT_B23P
R11
IO/DIFFIO_TX_B24P/DIFFOUT_B24P/DQ2B
V10
VCCIO3B
T8
VCCIO3B
V9
VREFB3BN0
U10
IC201BANK_3B
C308
100n, 6V3
C309
100n, 6V3
C310
4u7, 6V3
C311
10n, 6V3
C312
10n, 6V3
C313
10n, 6V3
C314
10n, 6V3
C315
10n, 6V3
C316
10n, 6V3
C317
4u7, 6V3
C318
100n, 6V3
R302
0R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
X302
IO_R3/2.2C
LVDS_RX_CLK_0_P
LVDS_RX_CLK_0_P
LVDS_RX_CLK_1_P
LVDS_RX_CLK_1_P
LVDS_RX_CLK_1_N
LVDS_RX_CLK_1_N
LVDS_TX_CLK_N
LVDS_TX_CLK_N
LVDS_TX_CLK_P
LVDS_TX_CLK_P
SATA_LVDS_TX_2_MCU_N/6.1B
SATA_LVDS_TX_2_MCU_P/6.1B
SATA_LVDS_RX_2_SPU_N/6.1A
SATA_LVDS_RX_2_SPU_P/6.1A
LVDS_RX_1_N
LVDS_RX_1_N
LVDS_RX_1_P
LVDS_RX_1_P
IO_T2/2.2C
IO_R2/2.2C
IO_R1/2.2B
IO_V8
IO_V8
LVDS_RX_3_P/2.2D
LVDS_RX_3_N/2.2D
IO_V6
IO_V6
IO_U5
IO_U5
IO_V7
IO_V7
IO_U4
IO_U4
IO_U8
IO_U8
IO_U7/2.2D
LVDS_RX_0_P
LVDS_RX_0_P
LVDS_RX_2_P/2.2E
LVDS_RX_2_N/2.2E
IO_T1/2.2C
LVDS_RX_0_N
LVDS_RX_0_N
LVDS_RX_CLK_0_N
LVDS_RX_CLK_0_N
IO_T10_P/4.3A
IO_T18_P/4.3B
IO_T18_N/4.3B
IO_T22_N/4.3C
IO_T10_N/4.3A
IO_T22_P/4.3C
IO_T16_P/4.3B
IO_T16_N/4.3B
IO_T12_P/4.3B
IO_T12_N/4.3B
VCCIO_VCCPD_SEL/8.7A
VCCIO_VCCPD_OUT
FPGA + I/O
A
B
C
D
E
1 2 3 4 5 6 7 8
A
B
C
D
E
1 2 3 4 5 6 7 8
abaxor engineering GmbH