Circuit diagram
MSEL0: 0 = fast, 1 = standard
enable INIT_DONE option
in Quartus Sotfware
5CEBA2U15
5CEBA2U15
5CEBA2U15
EPCQ32SI8N, alternativ N25Q032A13ESC
GND
GND
GND
GND
GND
LED-0603, green
GND
GND
GND
LED-0603, green, DNP
GND
GND
GND
PINHD-2X5
GND
+3V3
VCCIO_VCCPD
VCCIO_VCCPD
VCCPGM
VCCPGM
VCCPGM
VCCIO_VCCPD
GND
+3V3
2N7002P,225
VCCPGM
D1213A-02SOL-7
D1213A-02SOL-7
GND
GND
2N7002P,225, DNP
VCCIO_VCCPD
IO/DIFFIO_TX_L9N/DIFFOUT_L9N
E2
IO/DIFFIO_RX_L10N/DIFFOUT_L10N/DQ1L
J4
IO/DIFFIO_TX_L9P/DIFFOUT_L9P/DQ1L
D1
IO/DIFFIO_RX_L10P/DIFFOUT_L10P/DQ1L
J3
IO/DIFFIO_RX_L11N/DIFFOUT_L11N/DQSN1L
K2
IO/DIFFIO_TX_L12N/DIFFOUT_L12N/DQ1L
E3
IO/DIFFIO_RX_L11P/DIFFOUT_L11P/DQS1L
K3
IO/DIFFIO_TX_L12P/DIFFOUT_L12P
F2
IO/DIFFIO_TX_L13N/DIFFOUT_L13N/DQ1L
E1
IO/DIFFIO_RX_L14N/DIFFOUT_L14N/DQ1L
F4
IO/DIFFIO_TX_L13P/DIFFOUT_L13P/DQ1L
F1
IO/DIFFIO_RX_L14P/DIFFOUT_L14P/DQ1L
G3
IO/DIFFIO_RX_L15N/DIFFOUT_L15N
K1
O/DIFFIO_TX_L16N/DIFFOUT_L16N/DQ1L
H2
IO/DIFFIO_RX_L15P/DIFFOUT_L15P
L1
IO/DIFFIO_TX_L16P/DIFFOUT_L16P/DQ1L
G2
IO/DIFFIO_TX_L17N/DIFFOUT_L17N
J1
IO/DIFFIO_RX_L18N/DIFFOUT_L18N/DQ2L
L2
IO/DIFFIO_TX_L17P/DIFFOUT_L17P/DQ2L
H1
IO/DIFFIO_RX_L18P/DIFFOUT_L18P/DQ2L
M2
IO/DIFFIO_RX_L19N/DIFFOUT_L19N/DQSN2L
L5
IO/DIFFIO_TX_L20N/DIFFOUT_L20N/DQ2L
R1
IO/DIFFIO_RX_L19P/DIFFOUT_L19P/DQS2L
M4
IO/DIFFIO_TX_L20P/DIFFOUT_L20P
P1
IO/DIFFIO_TX_L21N/DIFFOUT_L21N/DQ2L
R2
IO/DIFFIO_RX_L22N/DIFFOUT_L22N/DQ2L
N2
IO/DIFFIO_TX_L21P/DIFFOUT_L21P/DQ2L
T1
IO/DIFFIO_RX_L22P/DIFFOUT_L22P/DQ2L
N3
IO/DIFFIO_RX_L23N/DIFFOUT_L23N
L4
IO/DIFFIO_TX_L24N/DIFFOUT_L24N/DQ2L
T2
IO/DIFFIO_RX_L23P/DIFFOUT_L23P
M3
IO/DIFFIO_TX_L24P/DIFFOUT_L24P/DQ2L
R3
VCCIO2A
H4
VCCIO2A
P2
VCCIO2A
L3
VCCIO2A
J2
VREFB2AN0
N1
IC201BANK_2A
TDO
P5
CSO/DATA4
P3
TMS
P6
AS_DATA3/DATA3
M5
TCK
L6
AS_DATA2/DATA2
U3
TDI
N6
AS_DATA1/DATA1
U2
DCLK
K6
AS_DATA0,ASDO/DATA0
V1
IO/DATA6/DIFFIO_RX_B1N/DIFFOUT_B1N/DQ1B
M7
IO/DATA5/DIFFIO_TX_B2N/DIFFOUT_B2N
V2
IO/DATA8/DIFFIO_RX_B1P/DIFFOUT_B1P/DQ1B
N7
IO/DATA7/DIFFIO_TX_B2P/DIFFOUT_B2P/DQ1B
V3
IO/DATA10/DIFFIO_RX_B3N/DIFFOUT_B3N/DQSN1B
M10
IO/DATA9/DIFFIO_TX_B4N/DIFFOUT_B4N/DQ1B
U7
IO/DATA12/DIFFIO_RX_B3P/DIFFOUT_B3P/DQS1B
N10
IO/DATA11/DIFFIO_TX_B4P/DIFFOUT_B4P
T7
IO/DATA14/DIFFIO_RX_B5N/DIFFOUT_B5N/DQ1B
M8
IO/DATA13/DIFFIO_TX_B6N/DIFFOUT_B6N/DQ1B
P4
IO/CLKUSR/DIFFIO_RX_B5P/DIFFOUT_B5P/DQ1B
M9
IO/DATA15/DIFFIO_TX_B6P/DIFFOUT_B6P/DQ1B
R4
IO/PR_DONE/DIFFIO_RX_B7N/DIFFOUT_B7N
N11
IO/PR_READY/DIFFIO_TX_B8N/DIFFOUT_B8N/DQ1B
P8
IO/PR_ERROR/DIFFIO_RX_B7P/DIFFOUT_B7P
P11
IO/DIFFIO_TX_B8P/DIFFOUT_B8P/DQ1B
N8
VCCIO3A
R5
VCCIO3A
U6
VREFB3AN0
V5
IC201BANK_3A
MSEL0
J6
CONF_DONE
C6
MSEL1
H5
STATUS
D6
CE
E4
MSEL2
D3
MSEL3
G5
CONFIG
D4
MSEL4
G4
GND
D5
IC201BANK_9A
GND
4
CS
1
DATA1
2
DATA2
3
DATA3
7
VCC
8
DCLK
6
IC202
DATA0
5
R212
10k
R213
10k
R214
10k
C201
100n, 6V3
C202
100n, 6V3
C204
100n, 6V3
C206
100n, 6V3
C208
4u7, 6V3
C203
100n, 6V3
C205
100n, 6V3
C207
4u7, 6V3
C210
100n, 6V3
LED_CONF
R215
220R
R209
0R
R210
0R, DNP
LED_INIT
R206
220R, DNP
R203
1k
R201
10k
R202
10k
R211
10k
JP201
1 2
3 4
5 6
7 8
9 10
R207
33k
R205
10k
R204
10k
R208
33k, DNP
C209
100n, 6V3
M201
D201
D202
M202
FPGA_DATA1
FPGA_DATA1
FPGA_CSO
FPGA_CSO
FPGA_STATUS
INIT_DONE
FPGA_TCK
FPGA_TCK
FPGA_TCK
FPGA_TMS
FPGA_TMS
FPGA_TMS
FPGA_TDO
FPGA_TDO
FPGA_TDO
FPGA_TDI
FPGA_TDI
FPGA_TDI
FPGA_DCLK
FPGA_DCLK
FPGA_CONF_DONEFPGA_CONF_DONE
FPGA_CONFIG
FPGA_DATA0
FPGA_DATA0
FPGA_CE
FPGA_DATA2
FPGA_DATA2
FPGA_DATA3
FPGA_DATA3
DBG_13/6.6D
DBG_9/6.4D
DBG_4/6.3D
DBG_12/6.6D
DBG_3/6.2D
DBG_8/6.4D
DBG_10/6.5D
DBG_15/6.6D
IO_T2/3.3E
IO_T1/3.4E
IO_R2/3.3E
IO_R1/3.4D
IO_R3/3.2E
IO_U7/3.4E
LVDS_RX_3_N/3.2E
LVDS_RX_3_P/3.2E
LVDS_RX_2_N/3.2E
LVDS_RX_2_P/3.2E
DBG_11/6.5D
DBG_14/6.6C
DBG_2/6.2D
DBG_5/6.3D
DBG_6/6.4D
FPGA Cofig
+ Debug IO
A
B
C
D
E
1 2 3 4 5 6 7 8
A
B
C
D
E
1 2 3 4 5 6 7 8
abaxor engineering GmbH