Data Sheet

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MCP3202

Features

• 12-bit resolution

• ±1 LSB max DNL

• ±1 LSB max INL (MCP3202-B)

• ±2 LSB max INL (MCP3202-C)

• Analog inputs programmable as single-ended or

pseudo-differential pairs

• On-chip sample and hold

• SPI serial interface (modes 0,0 and 1,1)

• Single supply operation: 2.7V-5.5V

• 100 ksps max. sampling rate at V

= 5V

• 50 ksps max. sampling rate at V

= 2.7V

• Low power CMOS technology

- 500 nA typical standby current, 5 μA max.

- 550 µA max. active current at 5V

• Industrial temp range: -40°C to +85°C

• 8-pin MSOP, PDIP, SOIC and TSSOP packages

Applications

• Sensor Interface

• Process Control

• Data Acquisition

• Battery Operated Systems

Description

The Microchip Technology Inc. MCP3202 is a succes-

sive approximation 12-bit Analog-to-Digital (A/D)

Converter with on-board sample and hold circuitry. The

MCP3202 is programmable to provide a single pseudo-

differential input pair or dual single-ended inputs. Differ-

ential Nonlinearity (DNL) is specified at ±1 LSB, and

Integral Nonlinearity (INL) is offered in ±1 LSB

(MCP3202-B) and ±2 LSB (MCP3202-C) versions.

Communication with the device is done using a simple

serial interface compatible with the SPI protocol. The

device is capable of conversion rates of up to 100 ksps

at 5V and 50 ksps at 2.7V. The MCP3202 device oper-

ates over a broad voltage range (2.7V-5.5V). Low-

current design permits operation with typical standby

and active currents of only 500 nA and 375 μA, respec-

tively. The MCP3202 is offered in 8-pin MSOP, PDIP,

TSSOP and 150 mil SOIC packages.

Package Types

Functional Block Diagram

MCP3202

CH0

CH1

CS/SHDN

REF

CLK

OUT

PDIP, MSOP, SOIC, TSSOP

Comparator

Sample

and

Hold

12-Bit SAR

DAC

Control Logic

CS/SHDN

CLK

OUT

Shift

CH0

Channel

Mux

Input

CH1

2.7V Dual Channel 12-Bit A/D Converter

with SPI Serial Interface

Summary of content (28 pages)

PAGE 1
MCP3202 2.7V Dual Channel 12-Bit A/D Converter with SPI Serial Interface Features • • • • • • • • 12-bit resolution ±1 LSB max DNL ±1 LSB max INL (MCP3202-B) ±2 LSB max INL (MCP3202-C) Analog inputs programmable as single-ended or pseudo-differential pairs On-chip sample and hold SPI serial interface (modes 0,0 and 1,1) Single supply operation: 2.7V-5.5V 100 ksps max. sampling rate at VDD = 5V 50 ksps max. sampling rate at VDD = 2.7V Low power CMOS technology - 500 nA typical standby current, 5 μA max.
PAGE 2
MCP3202 1.0 ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* PIN FUNCTION TABLE Name Function VDD/VREF +2.7V to 5.5V Power Supply and Reference Voltage Input All inputs and outputs w.r.t. VSS ...... -0.6V to VDD +0.6V CH0 Channel 0 Analog Input Storage temperature ..........................-65°C to +150°C CH1 Channel 1 Analog Input CLK Serial Clock DIN Serial Data In DOUT Serial Data Out CS/SHDN Chip Select/Shutdown Input VDD..............................................................
PAGE 3
MCP3202 ELECTRICAL CHARACTERISTICS (CONTINUED) All parameters apply at VDD = 5.5V, VSS = 0V, TAMB = -40°C to +85°C, fSAMPLE = 100 ksps and fCLK = 18*fSAMPLE unless otherwise noted.
PAGE 4
MCP3202 tCSH CS tSUCS tLO tHI CLK tSU DIN tHD MSB IN tEN DOUT tR tDO tDIS MSB OUT NULL BIT FIGURE 1-1: tF LSB Serial Timing. Load circuit for tDIS and tEN Load circuit for tR, tF, tDO Test Point 1.
PAGE 5
MCP3202 2.0 TYPICAL PERFORMANCE CHARACTERISTICS Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
PAGE 6
MCP3202 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE,TA = 25°C 1.0 1.0 0.8 VDD = 2.7V 0.6 0.6 FSAMPLE = 50 ksps 0.4 0.4 Positive INL INL (LSB) INL (LSB) 0.8 0.2 0.0 Negative INL -0.2 0.2 0.0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 Negative INL -1.0 -1.0 -50 -25 0 25 50 75 -50 100 -25 FIGURE 2-7: Temperature. Integral Nonlinearity (INL) vs. 25 50 FIGURE 2-10: Integral Nonlinearity Temperature (VDD = 2.7V). 1.0 2.0 0.8 1.
PAGE 7
MCP3202 1.0 1.0 0.8 0.8 V DD = 2.7V 0.6 0.6 FSAMPLE = 50 ksps 0.4 0.4 DNL (LSB) DNL (LSB) Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE,TA = 25°C 0.2 0.0 -0.2 -0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 Digital Code Digital Code FIGURE 2-13: Differential Nonlinearity Code (Representative Part). (DNL) vs.
PAGE 8
MCP3202 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE,TA = 25°C 1.0 2.0 1.8 V DD = 2.7V 0.6 Offset Error (LSB) Gain Error (LSB) 0.8 FSAMPLE = 50 ksps 0.4 0.2 0.0 -0.2 -0.4 -0.6 V DD = 5V -0.8 -50 -25 0 25 50 VDD = 5V 1.4 FSAMPLE = 100 ksps 1.2 1.0 0.8 VDD = 2.7V 0.6 FSAMPLE = 50 ksps 0.4 0.2 FSAMPLE = 100 ksps -1.0 1.6 75 0.0 -50 100 -25 0 FIGURE 2-19: Gain Error vs. Temperature. 75 100 FIGURE 2-22: Offset Error vs.
PAGE 9
MCP3202 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE,TA = 25°C 12.0 12.0 11.5 FSAMPLE = 100 ksps 11.0 ENOB (rms) ENOB (rms) VDD = 5V 11.5 FSAMPLE = 50ksps 11.0 FSAMPLE = 100 ksps 10.5 10.0 10.5 10.0 9.5 9.0 9.5 V DD = 2.7V 8.5 9.0 2.0 2.5 3.0 3.5 4.0 4.5 FSAMPLE = 50 ksps 8.0 5.0 1 10 VDD (V) FIGURE 2-25: Effective Number of Bits (ENOB) vs. VDD. FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency.
PAGE 10
MCP3202 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE,TA = 25°C 500 80 All points at FCLK = 1.8 MHz except 450 400 60 IDDS (pA) 350 IDD (µA) CS = V DD 70 at VDD = 2.5V, FCLK = 900 kHz 300 250 200 150 50 40 30 20 100 10 50 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.0 6.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 2-34: IDDS vs. VDD. FIGURE 2-31: IDD vs. VDD. 100.00 500 450 VDD = CS = 5V 400 V DD = 5V 10.
PAGE 11
MCP3202 3.0 PIN DESCRIPTIONS 4.1 3.1 CH0/CH1 The MCP3202 device offers the choice of using the analog input channels configured as two single-ended inputs or a single pseudo-differential input. Configuration is done as part of the serial command before each conversion begins. When used in the pseudo-differential mode, CH0 and CH1 are programmed as the IN+ and IN- inputs as part of the command string transmitted to the device. The IN+ input can range from IN- to VREF (VDD + IN-).
PAGE 12
MCP3202 VDD RSS VT = 0.6V CHx CPIN 7 pF VA Sampling Switch VT = 0.6V SS ILEAKAGE ±1 nA RS = 1 kΩ CSAMPLE = DAC capacitance = 20 pF VSS Legend VA RSS CHx CPIN VT ILEAKAGE SS RS CSAMPLE FIGURE 4-1: = = = = = = = = = signal source source impedance input channel pad input pin capacitance threshold voltage leakage current at the pin due to various junctions sampling switch sampling switch resistor sample/hold capacitance Analog Input Model. Clock Frequency (MHz) 2.0 1.8 VDD = 5V 1.6 1.4 1.2 1.
PAGE 13
MCP3202 5.0 SERIAL COMMUNICATIONS 5.1 Overview Communication with the MCP3202 is done using a standard SPI-compatible serial interface. Initiating communication with the device is done by bringing the CS line low. See Figure 5-1. If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and DIN high will constitute a start bit.
PAGE 14
MCP3202 tCYC tCSH CS tSUCS Power Down HI-Z DOUT tSAMPLE MSBF SGL/ DIFF ODD/ SIGN DIN Start CLK Don’t Care Null B11 B10 B9 Bit B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 *B10 B11 HI-Z (MSB) tCONV tDATA ** * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely.
PAGE 15
MCP3202 6.0 APPLICATIONS INFORMATION 6.1 Using the MCP3202 with Microcontroller (MCU) SPI Ports in the ‘low’ state, while Figure 6-2 shows the similar case of SPI Mode 1,1 where the clock idles in the ‘high’ state. As shown in Figure 6-1, the first byte transmitted to the A/D Converter contains seven leading zeros before the start bit. Arranging the leading zeros this way produces the output 12 bits to fall in positions easily manipulated by the MCU.
PAGE 16
MCP3202 6.2 Maintaining Minimum Clock Speed When the MCP3202 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample cap while the conversion is taking place. At 85°C (worst case condition), the part will maintain proper charge on the sample capacitor for at least 1.
PAGE 17
MCP3202 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 8-Lead PDIP (300 mil) MCP3202 e3 I/PNNN YYWW XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (150 mil) Example: MCP3202 e3 ISNYYWW NNN XXXXXXXX XXXXYYWW NNN Example: 8-Lead MSOP XXXXXX YWWNNN 3202I e3 YWWNNN Example: 8-Lead TSSOP XXXX YYWW NNN 3202 IYWW NNN Legend: XX...
PAGE 18
MCP3202 8-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 α E A2 A L c A1 β B1 p eB B Units Dimension Limits n p INCHES* NOM 8 .100 .155 .130 MAX MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MAX Number of Pins Pitch Top to Seating Plane A .140 .
PAGE 19
MCP3202 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil Body (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D 2 B n 1 h α 45° c A2 A φ β L Units Dimension Limits n p INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.
PAGE 20
MCP3202 8-Lead Plastic Micro Small Outline Package (MS) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 e b A2 A ϕ c L1 A1 Number of Pins Pitch Overall Height Molded Package Standoff Overall Width Molded Package Overall Length Foot Length Footprint Foot Angle Lead Thickness Lead Width Units Dimension Limits N e A Thickness A2 A1 E Width E1 D L L1 ϕ c b MIN — 0.75 0.00 0.
PAGE 21
MCP3202 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body (TSSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PAGE 23
MCP3202 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
PAGE 25
MCP3202 APPENDIX A: REVISION HISTORY Revision D (December 2006) This revision includes updates to the packaging diagrams. © 2006 Microchip Technology Inc.
PAGE 27
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 28
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