Data Sheet
Table Of Contents
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- Figure 2-1: DNL vs. Code.
- Figure 2-2: DNL vs. Code and Ambient Temperature.
- Figure 2-3: Absolute DNL vs. Ambient Temperature.
- Figure 2-4: INL vs. Code and Ambient Temperature.
- Figure 2-5: Absolute INL vs. Ambient Temperature.
- Figure 2-6: INL vs. Code.
- Figure 2-7: Full-Scale VOUTA w/G = 1 (VREF) vs. Ambient Temperature and VDD.
- Figure 2-8: Full-Scale VOUTA w/G = 2 (2VREF) vs.Ambient Temperature and VDD.
- Figure 2-9: Output Noise Voltage Density (VREF Noise Density w/G = 1) vs. Frequency.
- Figure 2-10: Output Noise Voltage (VREF Noise Voltage w/G = 1) vs. Bandwidth.
- Figure 2-11: MCP4821 IDD vs. Ambient Temperature and VDD.
- Figure 2-12: MCP4821 IDD Histogram (VDD = 2.7V).
- Figure 2-13: MCP4821 IDD Histogram (VDD = 5.0V).
- Figure 2-14: MCP4822 IDD vs. Ambient Temperature and VDD.
- Figure 2-15: MCP4822 IDD Histogram (VDD = 2.7V).
- Figure 2-16: MCP4822 IDD Histogram (VDD = 5.0V).
- Figure 2-17: Hardware Shutdown Current vs. Ambient Temperature and VDD.
- Figure 2-18: Software Shutdown Current vs. Ambient Temperature and VDD.
- Figure 2-19: Offset Error vs. Ambient Temperature and VDD.
- Figure 2-20: Gain Error vs. Ambient Temperature and VDD.
- Figure 2-21: VIN High Threshold vs. Ambient Temperature and VDD.
- Figure 2-22: VIN Low Threshold vs. Ambient Temperature and VDD.
- Figure 2-23: Input Hysteresis vs. Ambient Temperature and VDD.
- Figure 2-24: VOUT High Limit vs. Ambient Temperature and VDD.
- Figure 2-25: VOUT Low Limit vs. Ambient Temperature and VDD.
- Figure 2-26: IOUT High Short vs. Ambient Temperature and VDD.
- Figure 2-27: IOUT vs. VOUT. Gain = 2.
- Figure 2-28: VOUT Rise Time 100%.
- Figure 2-29: VOUT Fall Time.
- Figure 2-30: VOUT Rise Time 50%.
- Figure 2-31: VOUT Rise Time 25% - 75%.
- Figure 2-32: VOUT Rise Time Exit Shutdown.
- Figure 2-33: PSRR vs. Frequency.
- 3.0 Pin descriptions
- 4.0 General Overview
- 5.0 Serial Interface
- 6.0 Typical Applications
- 6.1 Digital Interface
- 6.2 Power Supply Considerations
- 6.3 Output Noise Considerations
- 6.4 Layout Considerations
- 6.5 Single-Supply Operation
- 6.6 Bipolar Operation
- 6.7 Selectable Gain and Offset Bipolar Voltage Output Using A Dual DAC
- 6.8 Designing A Double-Precision DAC Using A Dual DAC
- 6.9 Building A Programmable Current Source
- 7.0 Development support
- 8.0 Packaging Information
MCP4821/MCP4822
DS21953A-page 6 © 2005 Microchip Technology Inc.
AC CHARACTERISTICS (SPI™ TIMING SPECIFICATIONS)
FIGURE 1-1: SPI™ Input Timing.
Electrical Specifications: Unless otherwise indicated, V
DD
= 2.7V – 5.5V, T
A
= -40 to +125°C.
Typical values are at +25°C.
Parameters Sym Min Typ Max Units Conditions
Schmitt Trigger High-Level
Input Voltage
(All digital input pins)
V
IH
0.7 V
DD
——V
Schmitt Trigger Low-Level
Input Voltage
(All digital input pins)
V
IL
——0.2V
DD
V
Hysteresis of Schmitt Trigger
Inputs
V
HYS
—0.05V
DD
—
Input Leakage Current I
LEAKAGE
-1 — 1 μA SHDN = LDAC = CS = SDI =
SCK + V
REF
= V
DD
or AV
SS
Digital Pin Capacitance
(All inputs/outputs)
C
IN
,
C
OUT
—10—pFV
DD
= 5.0V, T
A
= +25°C,
f
CLK
= 1 MHz (Note 1)
Clock Frequency F
CLK
——20MHzT
A
= +25°C (Note 1)
Clock High Time t
HI
15 — — ns Note 1
Clock Low Time t
LO
15 — — ns Note 1
CS
Fall to First Rising CLK
Edge
t
CSSR
40 — — ns Applies only when CS falls with
CLK high. (Note 1)
Data Input Setup Time t
SU
15 — — ns Note 1
Data Input Hold Time t
HD
10 — — ns Note 1
SCK Rise to CS
Rise Hold
Time
t
CHS
15 — — ns Note 1
CS
High Time t
CSH
15 — — ns Note 1
LDAC
Pulse Width t
LD
100 — — ns Note 1
LDAC
Setup Time t
LS
40 — — ns Note 1
SCK Idle Time before CS
Fall t
IDLE
40 — — ns Note 1
Note 1: By design and characterization, not production tested.
CS
SCK
SI
LDAC
t
CSSR
t
HD
t
SU
t
LO
t
CSH
t
CHS
LSb in
MSb in
t
IDLE
Mode 1,1
Mode 0,0
t
HI
t
LD
t
LS