Data Sheet
Table Of Contents
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- Figure 2-1: DNL vs. Code.
- Figure 2-2: DNL vs. Code and Ambient Temperature.
- Figure 2-3: Absolute DNL vs. Ambient Temperature.
- Figure 2-4: INL vs. Code and Ambient Temperature.
- Figure 2-5: Absolute INL vs. Ambient Temperature.
- Figure 2-6: INL vs. Code.
- Figure 2-7: Full-Scale VOUTA w/G = 1 (VREF) vs. Ambient Temperature and VDD.
- Figure 2-8: Full-Scale VOUTA w/G = 2 (2VREF) vs.Ambient Temperature and VDD.
- Figure 2-9: Output Noise Voltage Density (VREF Noise Density w/G = 1) vs. Frequency.
- Figure 2-10: Output Noise Voltage (VREF Noise Voltage w/G = 1) vs. Bandwidth.
- Figure 2-11: MCP4821 IDD vs. Ambient Temperature and VDD.
- Figure 2-12: MCP4821 IDD Histogram (VDD = 2.7V).
- Figure 2-13: MCP4821 IDD Histogram (VDD = 5.0V).
- Figure 2-14: MCP4822 IDD vs. Ambient Temperature and VDD.
- Figure 2-15: MCP4822 IDD Histogram (VDD = 2.7V).
- Figure 2-16: MCP4822 IDD Histogram (VDD = 5.0V).
- Figure 2-17: Hardware Shutdown Current vs. Ambient Temperature and VDD.
- Figure 2-18: Software Shutdown Current vs. Ambient Temperature and VDD.
- Figure 2-19: Offset Error vs. Ambient Temperature and VDD.
- Figure 2-20: Gain Error vs. Ambient Temperature and VDD.
- Figure 2-21: VIN High Threshold vs. Ambient Temperature and VDD.
- Figure 2-22: VIN Low Threshold vs. Ambient Temperature and VDD.
- Figure 2-23: Input Hysteresis vs. Ambient Temperature and VDD.
- Figure 2-24: VOUT High Limit vs. Ambient Temperature and VDD.
- Figure 2-25: VOUT Low Limit vs. Ambient Temperature and VDD.
- Figure 2-26: IOUT High Short vs. Ambient Temperature and VDD.
- Figure 2-27: IOUT vs. VOUT. Gain = 2.
- Figure 2-28: VOUT Rise Time 100%.
- Figure 2-29: VOUT Fall Time.
- Figure 2-30: VOUT Rise Time 50%.
- Figure 2-31: VOUT Rise Time 25% - 75%.
- Figure 2-32: VOUT Rise Time Exit Shutdown.
- Figure 2-33: PSRR vs. Frequency.
- 3.0 Pin descriptions
- 4.0 General Overview
- 5.0 Serial Interface
- 6.0 Typical Applications
- 6.1 Digital Interface
- 6.2 Power Supply Considerations
- 6.3 Output Noise Considerations
- 6.4 Layout Considerations
- 6.5 Single-Supply Operation
- 6.6 Bipolar Operation
- 6.7 Selectable Gain and Offset Bipolar Voltage Output Using A Dual DAC
- 6.8 Designing A Double-Precision DAC Using A Dual DAC
- 6.9 Building A Programmable Current Source
- 7.0 Development support
- 8.0 Packaging Information
© 2005 Microchip Technology Inc. DS21953A-page 19
MCP4821/MCP4822
6.0 TYPICAL APPLICATIONS
The MCP482X devices are general purpose DACs
intended to be used in applications where a precision,
low-power DAC with moderate bandwidth and internal
voltage reference is required.
Applications generally suited for the MCP482X devices
include:
• Set Point or Offset Trimming
• Sensor Calibration
• Precision Selectable Voltage Reference
• Portable Instrumentation (Battery-Powered)
• Calibration of Optical Communication Devices
6.1 Digital Interface
The MCP482X devices utilize a 3-wire synchronous
serial protocol to transfer the DACs’ setup and output
values from the digital source. The serial protocol can
be interfaced to SPI™ or Microwire
peripherals com-
mon on many microcontroller units (MCUs), including
Microchip’s PICmicro
®
MCUs and dsPIC
®
DSC family
of MCUs. In addition to the three serial connections
(CS, SCK and SDI), the LDAC signal synchronizes
when the serial settings are latched into the DAC’s
output from the serial input latch. Figure 6-1 illustrates
the required connections. Note that LDAC
is active-low.
If desired, this input can be tied low to reduce the
required connections from 4 to 3. Write commands will
be latched directly into the output latch when a valid 16
clock transmission has been received and CS
has
been raised.
6.2 Power Supply Considerations
The typical application will require a bypass capacitor
in order to filter high-frequency noise. The noise can be
induced onto the power supply's traces or as a result of
changes on the DAC's output. The bypass capacitor
helps to minimize the effect of these noise sources on
signal integrity. Figure 6-1 illustrates an appropriate
bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as
close to the device power pin (V
DD
) as possible (within
4mm).
The power source supplying these devices should be
as clean as possible. If the application circuit has sep-
arate digital and analog power supplies, AV
DD
and
AV
SS
should reside on the analog plane.
6.3 Output Noise Considerations
The voltage noise density (in µV/√Hz) is illustrated in
Figure 2-9. This noise appears at V
OUTX
, and is prima-
rily a result of the internal reference voltage. Its 1/f
corner (f
CORNER
) is approximately 400 Hz.
Figure 2-10 illustrates the voltage noise (in mV
RMS
or
mV
P-P
). A small bypass capacitor on V
OUTX
is an
effective method to produce a single-pole Low-Pass
Filter (LPF) that will reduce this noise. For instance, a
bypass capacitor sized to produce a 1 kHz LPF would
result in an E
NREF
of about 100 µV
RMS
. This would be
necessary when trying to achieve the low DNL
performance (at G = 1) that the MCP482X devices are
capable of. The tested range for stability is .001µF thru
4.7 µF.
FIGURE 6-1: Typical Connection
Diagram.
6.4 Layout Considerations
Inductively-coupled AC transients and digital switching
noise can degrade the output signal integrity,
potentially masking the MCP482X family’s
performance. Careful board layout will minimize these
effects and increase the Signal-to-Noise Ratio (SNR).
Bench testing has shown that a multi-layer board
utilizing a low-inductance ground plane, isolated inputs,
isolated outputs and proper decoupling are critical to
achieving the performance that the MCP482X devices
are capable of providing. Particularly harsh
environments may require shielding of critical signals.
Breadboards and wire-wrapped boards are not
recommended if low noise is desired.
MCP482X
V
DD
V
DD
V
DD
AV
SS
AV
SS
AV
SS
V
OUTA
V
OUTB
MCP482X
0.1 µF
PICmicro
®
Microcontroller
0.1 µF 0.1 µF
V
OUTA
V
OUTB
SDI
SDI
CS
1
SDO
SCK
LDAC
CS
0
1µF
1µF