Data Sheet
Table Of Contents
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- Figure 2-1: DNL vs. Code.
- Figure 2-2: DNL vs. Code and Ambient Temperature.
- Figure 2-3: Absolute DNL vs. Ambient Temperature.
- Figure 2-4: INL vs. Code and Ambient Temperature.
- Figure 2-5: Absolute INL vs. Ambient Temperature.
- Figure 2-6: INL vs. Code.
- Figure 2-7: Full-Scale VOUTA w/G = 1 (VREF) vs. Ambient Temperature and VDD.
- Figure 2-8: Full-Scale VOUTA w/G = 2 (2VREF) vs.Ambient Temperature and VDD.
- Figure 2-9: Output Noise Voltage Density (VREF Noise Density w/G = 1) vs. Frequency.
- Figure 2-10: Output Noise Voltage (VREF Noise Voltage w/G = 1) vs. Bandwidth.
- Figure 2-11: MCP4821 IDD vs. Ambient Temperature and VDD.
- Figure 2-12: MCP4821 IDD Histogram (VDD = 2.7V).
- Figure 2-13: MCP4821 IDD Histogram (VDD = 5.0V).
- Figure 2-14: MCP4822 IDD vs. Ambient Temperature and VDD.
- Figure 2-15: MCP4822 IDD Histogram (VDD = 2.7V).
- Figure 2-16: MCP4822 IDD Histogram (VDD = 5.0V).
- Figure 2-17: Hardware Shutdown Current vs. Ambient Temperature and VDD.
- Figure 2-18: Software Shutdown Current vs. Ambient Temperature and VDD.
- Figure 2-19: Offset Error vs. Ambient Temperature and VDD.
- Figure 2-20: Gain Error vs. Ambient Temperature and VDD.
- Figure 2-21: VIN High Threshold vs. Ambient Temperature and VDD.
- Figure 2-22: VIN Low Threshold vs. Ambient Temperature and VDD.
- Figure 2-23: Input Hysteresis vs. Ambient Temperature and VDD.
- Figure 2-24: VOUT High Limit vs. Ambient Temperature and VDD.
- Figure 2-25: VOUT Low Limit vs. Ambient Temperature and VDD.
- Figure 2-26: IOUT High Short vs. Ambient Temperature and VDD.
- Figure 2-27: IOUT vs. VOUT. Gain = 2.
- Figure 2-28: VOUT Rise Time 100%.
- Figure 2-29: VOUT Fall Time.
- Figure 2-30: VOUT Rise Time 50%.
- Figure 2-31: VOUT Rise Time 25% - 75%.
- Figure 2-32: VOUT Rise Time Exit Shutdown.
- Figure 2-33: PSRR vs. Frequency.
- 3.0 Pin descriptions
- 4.0 General Overview
- 5.0 Serial Interface
- 6.0 Typical Applications
- 6.1 Digital Interface
- 6.2 Power Supply Considerations
- 6.3 Output Noise Considerations
- 6.4 Layout Considerations
- 6.5 Single-Supply Operation
- 6.6 Bipolar Operation
- 6.7 Selectable Gain and Offset Bipolar Voltage Output Using A Dual DAC
- 6.8 Designing A Double-Precision DAC Using A Dual DAC
- 6.9 Building A Programmable Current Source
- 7.0 Development support
- 8.0 Packaging Information
© 2005 Microchip Technology Inc. DS21953A-page 17
MCP4821/MCP4822
5.0 SERIAL INTERFACE
5.1 Overview
The MCP482X family is designed to interface directly
with the SPI port, available on many microcontrollers,
and supports Mode 0,0 and Mode 1,1. Commands and
data are sent to the device via the SDI pin, with data
being clocked-in on the rising edge of SCK. The
communications are unidirectional and, thus, data
cannot be read out of the MCP482X devices. The CS
pin must be held low for the duration of a write com-
mand. The write command consists of 16 bits and is
used to configure the DAC’s control and data latches.
Register 5-1 details the input registers used to
configure and load the DAC
A
and DAC
B
registers.
Refer to Figure 1-1 and the AC Electrical
Characteristics tables for detailed input and output tim-
ing specifications for both Mode 0,0 and Mode 1,1
operation.
5.2 Write Command
The write command is initiated by driving the CS pin
low, followed by clocking the four configuration bits and
the 12 data bits into the SDI pin on the rising edge of
SCK. The C
S pin is then raised, causing the data to be
latched into the selected DAC’s input registers. The
MCP482X devices utilize a double-buffered latch struc-
ture to allow both DAC
A
’s and DAC
B
’s outputs to be
synchronized with the LDAC
pin, if desired. Upon the
LDAC
pin achieving a low state, the values held in the
DAC’s input registers are transferred into the DACs’
output registers. The outputs will transition to the value
and held in the DAC
X
register.
All writes to the MCP482X devices are 16-bit words.
Any clocks past 16 will be ignored. The most signifi-
cant four bits are configuration bits. The remaining 12
bits are data bits. No data can be transferred into the
device with CS
high. This transfer will only occur if 16
clocks have been transferred into the device. If the
rising edge of CS
occurs prior, shifting of data into the
input registers will be aborted.
REGISTER 5-1: WRITE COMMAND REGISTER
bit 15 A/B: DAC
A
or DAC
B
Select bit
1 = Write to DAC
B
0 = Write to DAC
A
bit 14 — Don’t Care
bit 13 GA
: Output Gain Select bit
1 =1x (V
OUT
= V
REF
* D/4096)
0 =2x (V
OUT
= 2 * V
REF
* D/4096)
bit 12 SHDN
: Output Power-down Control bit
1 = Output Power-down Control bit
0 = Output buffer disabled, Output is high-impedance
bit 11-0 D11:D0: DAC Data bits
12-bit number “D” which sets the output value. Contains a value between 0 and 4095.
Upper Half:
W-x W-x W-x W-0 W-x W-x W-x W-x
A
/B — GA SHDN D11 D10 D9 D8
bit 15 bit 8
Lower Half:
W-x W-x W-x W-x W-x W-x W-x W-x
D7 D6 D5 D4
D3 D2 D1 D0
bit 7 bit 0
Legend
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown