Data Sheet
Table Of Contents
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- Figure 2-1: DNL vs. Code.
- Figure 2-2: DNL vs. Code and Ambient Temperature.
- Figure 2-3: Absolute DNL vs. Ambient Temperature.
- Figure 2-4: INL vs. Code and Ambient Temperature.
- Figure 2-5: Absolute INL vs. Ambient Temperature.
- Figure 2-6: INL vs. Code.
- Figure 2-7: Full-Scale VOUTA w/G = 1 (VREF) vs. Ambient Temperature and VDD.
- Figure 2-8: Full-Scale VOUTA w/G = 2 (2VREF) vs.Ambient Temperature and VDD.
- Figure 2-9: Output Noise Voltage Density (VREF Noise Density w/G = 1) vs. Frequency.
- Figure 2-10: Output Noise Voltage (VREF Noise Voltage w/G = 1) vs. Bandwidth.
- Figure 2-11: MCP4821 IDD vs. Ambient Temperature and VDD.
- Figure 2-12: MCP4821 IDD Histogram (VDD = 2.7V).
- Figure 2-13: MCP4821 IDD Histogram (VDD = 5.0V).
- Figure 2-14: MCP4822 IDD vs. Ambient Temperature and VDD.
- Figure 2-15: MCP4822 IDD Histogram (VDD = 2.7V).
- Figure 2-16: MCP4822 IDD Histogram (VDD = 5.0V).
- Figure 2-17: Hardware Shutdown Current vs. Ambient Temperature and VDD.
- Figure 2-18: Software Shutdown Current vs. Ambient Temperature and VDD.
- Figure 2-19: Offset Error vs. Ambient Temperature and VDD.
- Figure 2-20: Gain Error vs. Ambient Temperature and VDD.
- Figure 2-21: VIN High Threshold vs. Ambient Temperature and VDD.
- Figure 2-22: VIN Low Threshold vs. Ambient Temperature and VDD.
- Figure 2-23: Input Hysteresis vs. Ambient Temperature and VDD.
- Figure 2-24: VOUT High Limit vs. Ambient Temperature and VDD.
- Figure 2-25: VOUT Low Limit vs. Ambient Temperature and VDD.
- Figure 2-26: IOUT High Short vs. Ambient Temperature and VDD.
- Figure 2-27: IOUT vs. VOUT. Gain = 2.
- Figure 2-28: VOUT Rise Time 100%.
- Figure 2-29: VOUT Fall Time.
- Figure 2-30: VOUT Rise Time 50%.
- Figure 2-31: VOUT Rise Time 25% - 75%.
- Figure 2-32: VOUT Rise Time Exit Shutdown.
- Figure 2-33: PSRR vs. Frequency.
- 3.0 Pin descriptions
- 4.0 General Overview
- 5.0 Serial Interface
- 6.0 Typical Applications
- 6.1 Digital Interface
- 6.2 Power Supply Considerations
- 6.3 Output Noise Considerations
- 6.4 Layout Considerations
- 6.5 Single-Supply Operation
- 6.6 Bipolar Operation
- 6.7 Selectable Gain and Offset Bipolar Voltage Output Using A Dual DAC
- 6.8 Designing A Double-Precision DAC Using A Dual DAC
- 6.9 Building A Programmable Current Source
- 7.0 Development support
- 8.0 Packaging Information
MCP4821/MCP4822
DS21953A-page 16 © 2005 Microchip Technology Inc.
4.1 Circuit Descriptions
4.1.1 OUTPUT AMPLIFIERS
The DACs’ outputs are buffered with a low-power,
precision CMOS amplifier. This amplifier provides low
offset voltage and low noise. The output stage enables
the device to operate with output voltages close to the
power supply rails. Refer to Section 1.0 “Electrical
Characteristics” for range and load conditions.
In addition to resistive load-driving capability, the ampli-
fier will also drive high capacitive loads without oscilla-
tion. The amplifiers’ strong outputs allow V
OUT
to be
used as a programmable voltage reference in a
system.
4.1.1.1 Programmable Gain Block
The rail-to-rail output amplifier has configurable gain,
allowing optimal full-scale outputs for differing voltage
reference inputs. The output amplifier gain has two
selections, a gain of 1 V/V (GA
= 1) or a gain of 2 V/V
(GA
= 0).
The output range is ideally 0.000V to 4095/4096 *
2.048V when G = 1, and 0.000 to 4095/4096 * 4.096V
when G = 2. The default value for this bit is a gain of 2,
yielding an ideal full-scale output of 0.000V to 4.096V
due to the internal 2.048V V
REF
. Note that the near rail-
to-rail CMOS output buffer’s ability to approach AV
SS
and V
DD
establish practical range limitations. The
output swing specification in Section 1.0 “Electrical
Characteristics” defines the range for a given load
condition.
4.1.2 VOLTAGE REFERENCE
The MCP482X devices utilize internal 2.048V voltage
reference. The voltage reference has low temperature
coefficient and low noise characteristics. Refer to
Section 1.0 “Electrical Characteristics” for the
voltage reference specifications.
4.1.3 POWER-ON RESET CIRCUIT
The Power-On Reset (POR) circuit ensures that the
DACs power-up with SHDN
= 0 (high-impedance). The
devices will continue to have a high-impedance output
until a valid Write command is performed to either of
the DAC registers and the LDAC
pin meets the input
low threshold.
If the power supply voltage is less than the POR
threshold (V
POR
= 2.0V, typical), the DACs will be held
in their reset state. They will remain in that state until
V
DD
> V
POR
and a subsequent Write command is
received.
Figure 4-3 shows a typical power supply transient
pulse and the duration required to cause a reset to
occur, as well as the relationship between the duration
and trip voltage. A 0.1 µF decoupling capacitor,
mounted as close as possible to the V
DD
pin, provides
additional transient immunity.
FIGURE 4-3: Typical Transient Response.
4.1.4 SHUTDOWN MODE
Shutdown mode can be entered by using either hard-
ware or software commands. The hardware pin
(SHDN
) is only available on the MCP4821. During
Shutdown mode, the supply current is isolated from
most of the internal circuitry. The serial interface
remains active, thus allowing a Write command to
bring the device out of Shutdown mode. When the out-
put amplifiers are shut down, the feedback resistance
(typically 500 kΩ) produces a high-impedance path to
AV
SS
. The device will remain in Shutdown mode until
the SHDN
pin is brought high and a write command
with S
D = 1 is latched into the device. When a DAC is
changed from Shutdown to Active mode, the output
settling time takes < 10 µs, but greater than the
standard Active mode settling time (4.5 µs).
Transients above the curve
will cause a reset
Transients below the curve
will NOT cause a reset
5V
Time
Supply Voltages
Transient Duration
V
POR
V
DD
- V
POR
T
A
= +25°C
Transient Duration (µs)
10
8
6
4
2
0
12345
V
DD
– V
POR
(V)