MCP4821/MCP4822 12-Bit DACs with Internal VREF and SPI™ Interface Features Description • • • • • • • The Microchip Technology Inc. MCP482X devices are 2.7V–5.5V, low-power, low DNL, 12-bit Digital-to-Analog Converters (DACs) with internal band gap voltage reference, optional 2x-buffered output and Serial Peripheral Interface (SPI™).
MCP4821/MCP4822 1.0 ELECTRICAL CHARACTERISTICS † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings † VDD ................................................
MCP4821/MCP4822 5V AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x, RL = 5 kΩ to GND, CL = 100 pF, TA = -40 to +85°C. Typical values at +25°C. Parameters Sym Min Typ Max Units Conditions Output Swing VOUT — 0.010 to VDD – 0.040 — Phase Margin PM — 66 — ° Slew Rate SR — 0.55 — V/µs ISC — 15 24 mA tSETTLING — 4.
MCP4821/MCP4822 3V AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, VDD = 3V, AVSS = 0V, VREF = 2.048V external, output buffer gain (G) = 1x, RL = 5 kΩ to GND, CL = 100 pF, TA = -40 to +85°C. Typical values at 25°C Parameters Sym Min Typ Max Units Conditions VREF 2.008 2.048 2.088 V ΔVREF/°C — 125 325 ppm/°C -40°C to 0°C — 0.25 0.
MCP4821/MCP4822 5V EXTENDED TEMPERATURE SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x, RL = 5 kΩ to GND, CL = 100 pF. Typical values at +125°C by characterization or simulation. Parameters Sym Min Typ DNL (Note 1) DNL — ±0.25 — LSb Offset Error VOS — ±0.02 — % of FSR VOS/°C — -5 — ppm/°C gE — -0.10 — % of FSR ΔG/°C — -3 — ppm/°C VREF — 2.
MCP4821/MCP4822 AC CHARACTERISTICS (SPI™ TIMING SPECIFICATIONS) Electrical Specifications: Unless otherwise indicated, VDD= 2.7V – 5.5V, TA= -40 to +125°C. Typical values are at +25°C. Parameters Sym Min Typ Max Units Schmitt Trigger High-Level Input Voltage (All digital input pins) VIH 0.7 VDD — — V Schmitt Trigger Low-Level Input Voltage (All digital input pins) VIL — — 0.2 VDD V VHYS — 0.
MCP4821/MCP4822 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, AVSS = GND.
MCP4821/MCP4822 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
MCP4821/MCP4822 2.050 2.049 2.048 2.047 2.046 2.045 2.044 2.043 2.042 2.041 2.040 100 1.E-04 Output Noise Voltage Density (μV/Hz) Full Scale VOUT (V) Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 kΩ, CL = 100 pF. 10 1.E-05 VDD: 4V VDD: 3V VDD: 2.7V -40 -20 0 20 40 60 80 1 1.E-06 0.1 1.E-07 0.1 1E-1 100 120 1 1E+0 10 1E+1 FIGURE 2-7: Full-Scale VOUTA w/G = 1 (VREF) vs. Ambient Temperature and VDD. 4.
MCP4821/MCP4822 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 kΩ, CL = 100 pF. 5.5V 5.0V 4.0V 3.0V 2.7V VDD 320 IDD (μA) 300 280 260 240 600 5.5V 5.0V 4.0V 3.0V 2.7V VDD 550 500 IDD (μA) 340 450 400 220 350 200 180 300 -40 -20 0 20 40 60 80 100 120 -40 -20 FIGURE 2-11: MCP4821 IDD vs. Ambient Temperature and VDD. 20 40 80 100 120 FIGURE 2-14: MCP4822 IDD vs. Ambient Temperature and VDD.
MCP4821/MCP4822 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 kΩ, CL = 100 pF. 0.7 ISHDN (μA) 0.5 0.4 0.3 0.2 -0.05 -0.1 VDD -0.15 Gain Error (%) 5.5V 5.0V 4.0V 3.0V 2.7V VDD 0.6 5.5V 5.0V 4.0V 3.0V 2.7V -0.2 -0.25 -0.3 -0.35 -0.4 0.1 -0.45 -0.5 0 -40 -20 0 20 40 60 80 100 -40 120 -20 Ambient Temperature (ºC) FIGURE 2-17: Hardware Shutdown Current vs. Ambient Temperature and VDD. 4 40 60 80 100 120 3 4.0V 2.5 3.0V 2.
MCP4821/MCP4822 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 kΩ, CL = 100 pF. 16 2.5 5.5V 2 5.0V 1.75 1.5 4.0V 1.25 1 3.0V 2.7V 0.75 0.5 15 IOUT_HI_SHORTED (mA) VIN_SPI Hysteresis (V) 5.5V 5.0V 4.0V 3.0V 2.7V VDD 2.25 14 VDD 13 12 11 0.25 10 0 -40 -20 0 20 40 60 80 -40 100 120 -20 Ambient Temperature (ºC) FIGURE 2-23: Input Hysteresis vs. Ambient Temperature and VDD. 40 60 80 100 120 6.0 4.0V 0.033 5.0 0.
MCP4821/MCP4822 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 kΩ, CL = 100 pF. VOUT VOUT SCK LDAC LDAC Time (1 µs/div) FIGURE 2-28: VOUT Rise Time 100%. Time (1 µs/div) FIGURE 2-31: VOUT Rise Time 25% - 75%. VOUT VOUT SCK SCK LDAC LDAC Time (1 µs/div) VOUT Fall Time. FIGURE 2-32: Shutdown. VOUT SCK LDAC Time (1 µs/div) FIGURE 2-30: VOUT Rise Time Exit Ripple Rejection (dB) FIGURE 2-29: Time (1 µs/div) VOUT Rise Time 50%.
MCP4821/MCP4822 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP4821 Pin No. MCP4822 Pin No. Symbol 1 1 VDD Positive Power Supply Input (2.7V to 5.
MCP4821/MCP4822 4.0 GENERAL OVERVIEW INL < 0 The MCP482X devices are voltage-output string DACs. These devices include rail-to-rail output amplifiers, internal voltage reference, shutdown and reset-management circuitry. Serial communication conforms to the SPI protocol. The MCP482X devices operate from 2.7V to 5.5V supplies.
MCP4821/MCP4822 4.1.1 Circuit Descriptions OUTPUT AMPLIFIERS 5V Supply Voltages 4.1 The DACs’ outputs are buffered with a low-power, precision CMOS amplifier. This amplifier provides low offset voltage and low noise. The output stage enables the device to operate with output voltages close to the power supply rails. Refer to Section 1.0 “Electrical Characteristics” for range and load conditions.
MCP4821/MCP4822 5.0 SERIAL INTERFACE 5.1 Overview 5.2 The write command is initiated by driving the CS pin low, followed by clocking the four configuration bits and the 12 data bits into the SDI pin on the rising edge of SCK. The CS pin is then raised, causing the data to be latched into the selected DAC’s input registers. The MCP482X devices utilize a double-buffered latch structure to allow both DACA’s and DACB’s outputs to be synchronized with the LDAC pin, if desired.
MCP4821/MCP4822 CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK (Mode 0,0) config bits SDI (Mode 1,1) A/B 12 data bits — GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LDAC VOUT FIGURE 5-1: DS21953A-page 18 Write Command. © 2005 Microchip Technology Inc.
MCP4821/MCP4822 6.0 TYPICAL APPLICATIONS 6.3 Output Noise Considerations The MCP482X devices are general purpose DACs intended to be used in applications where a precision, low-power DAC with moderate bandwidth and internal voltage reference is required. The voltage noise density (in µV/√Hz) is illustrated in Figure 2-9. This noise appears at VOUTX, and is primarily a result of the internal reference voltage. Its 1/f corner (fCORNER) is approximately 400 Hz.
MCP4821/MCP4822 6.5 6.5.1.1 Single-Supply Operation If the application is calibrating the threshold of a diode, transistor or resistor tied to AVSS, a threshold range of 0.8V may be desired to provide 200 µV resolution. Two common methods to achieve a 0.8V range is to either reduce VREF to 0.82V (would require MCP492X device and external voltage reference) or use a voltage divider on the DAC’s output. Typically, when using a lowvoltage VREF, the noise floor causes SNR error that is intolerable.
MCP4821/MCP4822 6.5.1.2 Building a “Window” DAC creating a “window” around the threshold has several advantages. One simple method to create this “window” is to use a voltage divider network with a pullup and pull-down resistor. Example 6-2 and Example 6-4 illustrates this concept. When calibrating a set point or threshold of a sensor, rarely does the sensor utilize the entire output range of the DAC.
MCP4821/MCP4822 6.6 Bipolar Operation Example 6-3 illustrates a simple bipolar voltage source configuration. R1 and R2 allow the gain to be selected, while R3 and R4 shift the DAC's output to a selected offset. Note that R4 can be tied to VDD, instead of AVSS, if a higher offset is desired. Note that a pull-up to VDD could be used, instead of R4 or in addition to R4, if a higher offset is desired.
MCP4821/MCP4822 6.7 Selectable Gain and Offset Bipolar Voltage Output Using A Dual DAC In some applications, precision digital control of the output range is desirable. Example 6-4 illustrates how to use the MCP482X family to achieve this in a bipolar or single-supply application. This circuit is typically used for linearizing a sensor whose slope and offset varies. The equation to design a bipolar “window” DAC would be utilized if R3, R4 and R5 are populated.
MCP4821/MCP4822 6.8 Designing A Double-Precision DAC Using A Dual DAC 1. Example 6-5 illustrates how to design a single-supply voltage output capable of up to 24-bit resolution from a dual 12-bit DAC. This design is simply a voltage divider with a buffered output. 2. As an example, if a similar application to the one developed in Section 6.6.1 “Design a Bipolar DAC Using Example 6-3” required a resolution of 1 µV instead of 1 mV, and a range of 0V to 4.1V, then 12-bit resolution would not be adequate.
MCP4821/MCP4822 6.9 Building A Programmable Current Source Example 6-6 illustrates a variation on a voltage follower design where a sense resistor is used to convert the DAC’s voltage output into a digitally-selectable current source. Adding the resistor network from Example 6-2 would be advantageous in this application. The smaller RSENSE is, the less power dissipated across it. However, this also reduces the resolution that the current can be controlled with.
MCP4821/MCP4822 7.0 DEVELOPMENT SUPPORT 7.1 Evaluation & Demonstration Boards The Mixed Signal PICtail™ Demo Board supports the MCP482X family of devices. Refer to www.microchip.com for further information on this product’s capabilities and availability. DS21953A-page 26 7.2 Application Notes Application notes illustrating the performance and implementation of the MCP482X family are planned but are currently not released. Refer to www.microchip.com for further information.
MCP4821/MCP4822 8.0 PACKAGING INFORMATION 8.1 Package Marking Information Example: 8-Lead MSOP XXXXXX YWWNNN 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW Legend: XX...
MCP4821/MCP4822 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p D 2 B n 1 α A2 A c φ A1 (F) L β Units Dimension Limits n p MIN INCHES NOM MAX MILLIMETERS* NOM 8 0.65 BSC 0.75 0.85 0.00 4.90 BSC 3.00 BSC 3.00 BSC 0.40 0.60 0.95 REF 0° 0.08 0.22 5° 5° - MIN 8 Number of Pins .026 BSC Pitch A .043 Overall Height A2 .030 .033 .037 Molded Package Thickness .006 .000 A1 Standoff E .193 TYP. Overall Width E1 .118 BSC Molded Package Width .118 BSC D Overall Length L .016 .024 .
MCP4821/MCP4822 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic § A A2 A1 E E1 D L c B1 B
MCP4821/MCP4822 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .146 .189 .010 .
MCP4821/4822 APPENDIX A: REVISION HISTORY Revision A (June 2005) • Original Release of this Document. © 2005 Microchip Technology Inc.
MCP4821/4822 NOTES: DS21953A-page 32 © 2005 Microchip Technology Inc.
MCP4821/4822 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
MCP4821/4822 NOTES: DS21953A-page 34 © 2005 Microchip Technology Inc.
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