Data Sheet

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PCA9685 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 — 2 September 2010 40 of 51 NXP Semiconductors
PCA9685
16-channel, 12-bit PWM Fm+ I
2
C-bus LED controller
[1] Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held LOW for a minimum of 25 ms.
Disable bus time-out feature for DC operation.
[2] t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[3] t
VD;DAT
= minimum time for SDA data out to be valid following SCL LOW.
[4] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
IL
of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
[5] The maximum t
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (t
f
) for the SDA output stage is specified at 250 ns. This allows series
protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t
f
.
[6] C
b
= total capacitance of one bus line in pF.
[7] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
t
PZH
OFF-state to HIGH propagation
delay
OE to LEDn;
OUTNE[1:0] = 10 or 11
in MODE2 register
-40 - 40-40ns
t
PLH
LOW to HIGH propagation delay OE to LEDn;
OUTNE[1:0] = 01
in MODE2 register
-40 - 40-40ns
t
PHL
HIGH to LOW propagation delay OE to LEDn;
OUTNE[1:0] = 00
in MODE2 register
-60 - 60-60ns
Table 14. Dynamic characteristics
…continued
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode I
2
C-bus Fast-mode Plus
I
2
C-bus
Unit
Min Max Min Max Min Max