System information

FCD 901 48

Issue R2A, 07.2009

XMP1 Release 5.5 System Description

Suppressing the clock priority (at F1in)

Aastra Proprietary Information Page 2-25

Example 2:

In the following example, transmission between XMP1 nodes 1 and 2 takes

place via two SDH multiplexers. In these multiplexers, a retiming process is

performed for the 2 Mbit/s signal. Thus, XMP1 node 2 receives a clock

different from the one supplied by XMP1 node 1. This also applies to XMP1

node 1. For this reason, the clock priority at F1in must be suppressed at the

port of XMP1 node 1 and 2 using info no. 10.

XMP1 node 1

XMP1 node 2

SDH multiplexer 1

SDH multiplexer 2

Port

Retiming

Info no. 10: "1"

2 Mbit/s

STM-1