System information

FCD 901 48
Issue R2A, 07.2009
XMP1 Release 5.5 System Description
Delay time reduction in linear networks
Aastra Proprietary Information Page 2-21
2.3.6.6 Delay time reduction in linear networks
In linear networks, the delay time of the port can be reduced by about 60 µs
compared with the statistical average value.
This setting is made in the decentral card slot data of the ports using info
no. 14 "Short delay time in a linear network".
However, this function is also possible on line sections in meshed networks
or star networks. With short delay times adjusted, line breaks or clock
source switchovers will first lead to an increased number of frame slips
before the most favorable phase position for short delay times is achieved.
For this reason, this delay time reduction option should be enabled only if
required.
In nodes where lines from at least three directions are received and meshes
are therefore formed, this function is not recommended. In this case, the
network becomes relatively sensitive to jitter and clock switchovers and an
increased number of frame slips have to be expected.
This function should be activated only in conjunction with the following
Central Units.
The Central Units offer a hardware considerably improved for this function.
On all other Central Units, processes are much more complex so that the
use of the described function is not recommended.
Tab. 2.I: Central Units for delay time reduction
Central Unit CC/QD2 62.7040.310.00-A001 AN00102460
Central Unit CC 62.7040.320.00-A001 AN00102461
Central Unit GN 62.7040.330.00-A001 AN00102462
Central Unit GN/QD2 62.7040.355.00-A001 AN00239607