FCD 901 48
Issue R2A, 07.2009
XMP1 Release 5.5 System Description
Clock priority control
Page 2-16 Proprietary Information Aastra
Port 1
Port 2
Port 16
T3in
2048 kHz
T
INT
2048 kHz
PLL
Central Unit
T3out
System clock
Rx
clock 1
Rx
clock 2
Rx
clock 16
F1in
F1in
F1in
T3in
ISDN
UK0Q
TE
Tin
T3in
S0
SDH clock T0
