System information

FCD 901 48
Issue R2A, 07.2009
XMP1 Release 5.5 System Description
Clock priority control
Aastra Proprietary Information Page 2-15
2.3.3 Clock priority control
To control clock priorities, the number of the highest clock priority of the
PCM network is sent out.
The clock priority is transmitted in bit Y5 of the service digits.
Each network node continuously polls the Y5 bits of the frame alignment
signal of its ports and verifies as to whether it receives at one of its ports a
clock priority higher than its own highest clock priority.
In this case, it sends out the clock priority received at all ports in the
downward direction.
If the node has a higher priority than the one received, it sends out its own
highest priority at all ports and assumes thus clock control of the PCM
network. The clock priority thus accompanies the clock all the way through
the network.
In case of an interruption of individual connections, the clock source with the
highest priority will be used in the entire network still addressable. If - due
to an interruption - the network is split up into individual isolated
sub-networks, the clock source with the highest priority will be used within
the latter.
The prerequisite for this clock control via the clock priority is that the
connection between two network nodes is clock-transparent. If clock
transparency is not ensured for this connection or for only one direction,
clock priority evaluation must be suppressed at both or at one of the ports.
The clock priority at an XMP1 port must thus be suppressed whenever a
port receives a clock different from that injected into the far-end XMP1 port.
This evaluation of the clock priority at F1in of a port can be suppressed. This
is possible via info no. 10 of the decentral card slot data of the port modules.
If this info is set to "1", the Y5 bit available at this port is no longer evaluated
as described above. Also see Section 2.3.6.8, Suppressing the clock
priority (at F1in) .
Figure 2.6: Clock distribution