System information

FCD 901 48
Issue R2A, 07.2009
XMP1 Release 5.5 System Description
Assignment of clock priorities
Page 2-14 Proprietary Information Aastra
The ports of clock interfaces T3in and T3out (T4) are implemented on a
9-pin D-Sub connector (male) of the Central Unit or - with the SDH
expansion - on the the SCU module.
Receive clocks at ports
The 2 Mbit/s signals available at F1 inputs of the ports are used to recover
the receive clock. For this purpose, the ports transmit their F1in sum signal
via the TE clock line to the Central Unit. In doing so, they are controlled by
the clock priority. In the Central Unit, the clock is recovered from this sum
signal and used as system clock.
ISDN clock
In this case, clock recovery takes place using the receive clock of the ISDN
interface (S0 or Uko).
SDH clock T0
For synchronization purposes, the SDH clock made available by the SDH
expansion can also be used. See Section 3.6, Clock Supply .
2.3.2 Assignment of clock priorities
During configuration, each clock source available in an XMP1 network can
be assigned a clock priority. This clock priority assignment takes place using
the clock priority list. A node can have many clock sources which can be
assigned a clock priority.
These clock sources can be the following:
• internal clock,
• external T3in clock,
• recovered receive clocks of the ports (maximally 16)
and ISDN clock.
•SDH clock
If the operator does not assign a priority to all internal clock sources, these
will be assigned a clock priority by the system. These priorities will be
counted down from 65534.
All other clock sources without any priority will be automatically assigned
priority 65535 by the system.
Up to 65534 clock priorities can be allocated in a PCM network.